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iqx family data sheet february 2001 revision 6.2 1 f eatures ? sram-based, in-system programmable switch matrix ? non-blocking ? identical and predictable delays ? one-to-one, one-to-many and many-to-one connections rapidconfigure ? parallel interface for fast, incremental configuration of switch matrix and i/o port attributes ? 100% jtag compliant clocked, latched and flow-through dataflow modes ? as low as 7.5 ns pin-to-pin delay in flow-through mode and 133 mhz clock rate in registered mode i/o ports ? individually programmable as input, output or bidirectional ? for each i/o port, clock, clock enable, input enable and output enable can be selected independently from a large pool of common control signals ? 12 ma current drive ? separated i/o power pins for easy interfacing between 5v and 3.3v signals d escription the iqx family of sram-based bit-oriented switching devices is manufactured using a 0.6 m cmos process. these devices offer clock speeds of up to 133 mhz and pin-to-pin delay as low as 7.5 ns. the iqx devices are used in applications requiring dynamic switching and flexible routing / interconnection of signals. these applications include communication switches, network systems, dsp / image processing engines and file/video servers. at the heart of iqx devices is a non-blocking switch matrix. a line in the switch matrix can be connected to one or more other lines. the switch matrix lines are connected to i/o ports with programmable functional attributes. the rapidconfigure parallel interface allows connections in the switch matrix to be changed quickly and incrementally. this interface can also be used to configure i/o port attributes individually and incrementally. in either case, data integrity is maintained on all unchanged signal paths through the device. the iqx devices support the industry standard jtag (ieee 1149.1) interface for boundary scan testing. the same interface can also used for serially downloading the configuration bit stream into the devices. figure 1. iqx functional block diagram i/o port i/o control switch matrix [crossbar array] jtag configuration control signal ports tdi tms tck tdo i/o port i/o port rapidconfigure interface i/o port i/o port i/o port i/o port shared with i/o control signals dedicated i/o control signals trst* shared with rapidconfigure interface signals
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contents february 2001 revision 6.2 3 features ....................................................................................................................... .................................1 description.................................................................................................................... ...............................1 1.0 architecture .............................................................................................................. ............................9 1.1 non-blocking switch matrix ................................................................................................ ..........9 1.1.1 switch control ......................................................................................................... .............9 1.2 programmable i/o port ..................................................................................................... ............10 1.2.1 programmable pull-up current ............................................................................................ 10 1.2.2 pin and array side trickle current .....................................................................................1 0 1.2.3 i/o port functional mode ................................................................................................ ....10 1.3 i/o control signals ....................................................................................................... ................14 1.3.1 clock control........................................................................................................... ............15 1.3.2 tristate control ........................................................................................................ ............15 1.3.3 neighboring i/o port as a control source.........................................................................15 1.3.4 key control pins as a control source .................................................................................15 1.3.5 default values for control signals...................................................................................... 15 1.4 rapidconfigure (rc) interface ............................................................................................. .......15 1.4.1 switch matrix connection changes ....................................................................................16 1.4.2 i/o port configuration .................................................................................................. .......18 1.4.3 i/o port configuration holding register.............................................................................18 1.4.4 i/o port configuration register contents ...........................................................................21 1.4.5 reset commands .......................................................................................................... .......21 1.5 jtag-based configuration controller ....................................................................................... ..22 1.5.1 jtag interface .......................................................................................................... ..........22 1.5.2 i/o port configuration .................................................................................................. .......22 1.5.3 switch matrix configuration ............................................................................................. ..22 1.5.4 mode control register configuration .................................................................................22 2.1 device reset .............................................................................................................. ...................23 2.2 mixed voltage operation ................................................................................................... ..........23 2.3 power pin v dd .x..........................................................................................................................23 2.4 mode control register..................................................................................................... .............24 3.0 in system configuration using jtag-based configuration controller ............................................25 3.1 bit stream generation ..................................................................................................... .............25 3.2 bit stream downloading .................................................................................................... ..........25 3.3 configuring multiple iqx devices .......................................................................................... ....26 4.0 pin summary............................................................................................................... ........................27 5.0 electrical specifications ................................................................................................. ....................29 5.1 absolute maximum ratings (1) ........................................................................................... .....29 5.2 recommended operating conditions ....................................................................................... .29 5.3 capacitance (3) ........................................................................................................ ..................29 5.4 dc electrical specifications .............................................................................................. ...........30 5.5 ac electrical specifications for iqx320 and iqx240b..............................................................31
contents 4 revision 6.2 february 2000 5.6 ac electrical specifications for iqx160 and iqx128b..............................................................33 5.7 parameter de-rating for one-to-many connections....................................................................35 5.8 test circuit and timing diagrams .......................................................................................... .....36 6.0 pinout .................................................................................................................... ..............................43 6.1 iqx320 [pbga/416l] package pinout by name ........................................................................43 6.2 iqx320 [pbga/416l] package pinout by location ...................................................................44 6.3 iqx320 [pbga/416l] package footprint ...................................................................................45 6.4 iqx240b [pqfp/304l] package pinout by name .......................................................................46 6.5 iqx240b [pqfp/304l] package pinout by location ..................................................................47 6.6 iqx240b [pqfp/304l] package pinout ......................................................................................48 6.7 iqx160 [pqfp/208l] package pinout by name .........................................................................49 6.8 iqx160 [pqfp/208l] package pinout by location ....................................................................50 6.9 iqx160 [pqfp/208l] package pinout......................................................................................... 51 6.10 iqx128b [pqfp/184l] package pinout by name.....................................................................52 6.11 iqx128b [pqfp/184l] package pinout by location ................................................................53 6.12 iqx128b [pqfp/184l] package pinout ....................................................................................54 7.0 mechanical specification.................................................................................................. ..................55 7.1 iqx320 [pbga/416l] package dimensions ...............................................................................55 7.2 pqfp package dimensions .................................................................................................. .......56 8.0 package thermal characteristics........................................................................................... .............57 9.0 tables for determining die pad to i/o port pin mapping and locations of real sram cell ....... 58 10.0 component availability and ordering information .........................................................................6 2 11.0 iqx family at a glance ................................................................................................... .................63 12.0 revision history ......................................................................................................... ......................64 13.0 product status definitions ............................................................................................... .................65
figures february 2001 revision 6.2 5 figure 1. iqx functional block diagram ........................................................................................ ..........1 figure 2. switch matrix structure ............................................................................................. .................9 figure 3. switch matrix control............................................................................................... ................10 figure 4. programmable i/o port ............................................................................................... ..............10 figure 5. iqx output driver and pull-up current............................................................................... ....10 figure 6. i/o control ......................................................................................................... .......................14 figure 7. iqx rapidconfigure system interface ................................................................................. ....16 figure 8. reset circuit ....................................................................................................... .......................23 figure 9. off-line bit stream generation ...................................................................................... ...........25 figure 10. embedded bit stream generation ..................................................................................... ......25 figure 11. configuring multiple iqx devices................................................................................... ......26 figure 12. test circuit and waveform definition............................................................................... .....36 figure 13. registered input and registered output mode timing (iclk, oclk synchronized)..........36 figure 14. registered input mode timing ....................................................................................... ........36 figure 15. registered output mode timing...................................................................................... .......37 figure 16. i/o port timing (flow ? through mode)...................................................................................37 figure 17. input enable timing (flow ? through mode) ...........................................................................37 figure 18. output enable timing (flow ? through mode) ........................................................................38 figure 19. latched input mode timing.......................................................................................... ..........38 figure 20. latched output mode timing ......................................................................................... ........38 figure 21. key timing for register input, clock enable (cke).............................................................39 figure 22. key timing for register output, clock enable (cke) ..........................................................39 figure 23. key timing for input enable ........................................................................................ ..........39 figure 24. key timing for output enable....................................................................................... .........40 figure 25. key timing for latch input, enable (cke)........................................................................... .40 figure 26. key timing for latch output, enable (cke) .........................................................................4 0 figure 27. key counter timing................................................................................................. ...............41 figure 28. rapidconfigure timing .............................................................................................. ............41 figure 29. jtag timing ........................................................................................................ ..................42 figure 30. iqx320 [pbga/416l] package footprint..............................................................................4 5 figure 31. iqx240b [ pqfp/ 304l] package pinout ..................................................................................48 figure 32. iqx160 [pqfp/208l] package pinout .................................................................................. .51 figure 33. iqx128b [pqfp/184l] package pinout................................................................................. 54 figure 34. iqx320 [pbga/416l] package dimensions..........................................................................55 figure 35. pqfp package dimensions ............................................................................................ .........56
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tables february 2001 revision 6.2 7 table 1. summary of programmable i/o attributes for iqx devices .....................................................11 table 2. rapidconfigure interface pin count ................................................................................... .......16 table 3. rapidconfigure options ............................................................................................... ..............16 table 4. changing switch matrix connections using rapidconfigure ..................................................17 table 5. configuring i/o ports using rapidconfigure interface.............................................................18 table 6. i/o port configuration bits .......................................................................................... ..............19 table 7. i/o configuration register contents .................................................................................. ........21 table 8. rapidconfigure reset commands ........................................................................................ .....22 table 9. device reset ......................................................................................................... ......................23 table 10. mode control register bit assignment ................................................................................ ...24 table 11. number of jtag cycles and configuration time (using a 10 mhz jtag clock) ................26 table 12. iqx pin summary .................................................................................................... ...............27 table 13. supply voltage source ............................................................................................... ..............28 table 14. absolute maximum ratings ............................................................................................ .........29 table 15. recommended operating conditions.................................................................................... ...29 table 16. capacitance......................................................................................................... ......................29 table 17. dc electrical specifications........................................................................................ .............30 table 18. ac electrical specifications for iqx320 and iqx240b..........................................................31 table 19. ac electrical specifications for iqx160 and iqx128b..........................................................33 table 20. parameter de-rating for one-to-many connections................................................................35 table 21. iqx320 [pbga/416l] package pinout by name ....................................................................43 table 22. iqx320 [pbga/416l] package pinout by location ...............................................................44 table 23. iqx240b [pqfp/304l] package pinout by name ..................................................................46 table 24. iqx240b [pqfp/304l] package pinout by location..............................................................47 table 25. iqx160 [pqfp/208l] package pinout by name .....................................................................49 table 26. iqx160 [pqfp/208l] package pinout by location ................................................................50 table 27. iqx128b [pqfp/184l] package pinout by name ..................................................................52 table 28. iqx128b [pqfp/184l] package pinout by location..............................................................53 table 29. pqfp package dimensions ............................................................................................. .........56 table 30. package thermal coefficients ........................................................................................ ..........57 table 31. iqx320 and iqx240b i/o port pin mapping ..........................................................................59 table 32. iqx160 and iqx128b i/o port pin mapping ..........................................................................61 table 33. component availability.............................................................................................. ..............62 table 34. ordering information................................................................................................ ................62 table 35. iqx family at a glance .............................................................................................. ..............63 table 36. revision history .................................................................................................... ...................64
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iqx family data sheet february 2001 revision 6.2 9 1.0 a rchitecture iqx devices are sram-based bit-oriented switching matrices. the devices can be configured and controlled in-system by storing appropriate data into the internal sram cells and configuration registers. as shown in figure 1, the main functional blocks of the device are the non-blocking switch matrix, programmable i/o ports, i/o control signal block, rapidconfigure configuration interface and a jtag-based configuration controller. the full-featured programmable i/o ports are connected to the corresponding lines in the switch matrix. the i/o port control signals such as clock, clock enable, input enable, and output enable are used to control the flow of data through the i/o ports. the jtag-based configuration controller is used to download the configuration bit stream serially into the i/o port configuration registers and switch matrix sram cells, thereby establishing the desired functional attributes for the i/o ports and connections among them through the switch matrix. alternatively, the rapidconfigure parallel interface may be used to load the configuration data in the i/o port configuration registers and switch matrix sram cells. the use of rapidconfigure interface enables quick configuration changes. 1.1 non-blocking switch matrix the switch matrix is an x-y routing structure (or grid). each horizontal signal trace is hardwired to a corresponding vertical signal trace as shown by the junction dots in figure 2. an i/o port pin connects to this horizontal-vertical trace pair through a programmable buffer. signal paths through the switch matrix are very well balanced, resulting in predictable and uniform pin-to- pin delays. a pass transistor whose on/off state is controlled by a dedicated sram cell is placed at the intersection of two different signal lines. signal multicasting/broadcasting operation is supported by allowing a switch matrix line carrying an incoming signal to be connected to multiple switch matrix lines carrying outgoing signals. signal multiplexing is supported by allowing multiple switch matrix lines carrying incoming signals (controlled using input enable signals) to be connected to the same switch matrix line carrying an outgoing signal. it is also possible to create a common internal node among multiple switch matrix lines by making all pair-wise connections among these signal lines, and driving such a node by configuring the corresponding i/o ports in the bus repeater mode. refer to the section on ? i/o port functional mode ? for more details. figure 2. switch matrix structure 1.1.1 switch control as shown in figure 3, there are two possible switch and sram cell locations for a connection between any two switch matrix lines. for example, the two possible switch (and sram cell) locations controlling a connection between signal lines i and j are row i (word i) and column j (bit j), or row j and column i. only one location is populated with a switch and the controlling sram cell. this location is called the real location while the other one is referred to as the ghost location. the real cell locations form a unique pattern on the device die as described in appendix a. the section on ? rapidconfigure interface ? explains how this knowledge can be used to reduce the time it takes to change switch matrix connections. 1 0 2 34 567 i/o port pins sram cells pass transistors signal lines permanent connections programmable i/o buffers
iqx family data sheet 10 revision 6.2 february 2001 figure 3. switch matrix control 1.2 programmable i/o port each signal line in the switch matrix is connected to a programmable i/o port. the functional attributes of individual i/o ports can be programmed independently. the i/o port attributes include its signal direction (in, out or bidirectional), data flow mode (flow-through, registered or latched), and pull-up current. figure 4 shows the structure of the programmable i/o port. the sources for the four control signals: clock (clk), clock enable (cke), input enable (ie), and output enable (oe ) are also programmable and are described later in the section ? i/o control signals. ? figure 4. programmable i/o port 1.2.1 programmable pull-up current as shown in figure 5, the i/o port contains several n-channel pull-up devices. the normal pull-up current is supplied by a device which is switched on/off by internally generated control signal. an additional static pull-up current (i pu-wk ) or (i pu-sg ) can be programmed at each i/o port pin. this additional pull-up current is primarily used for but not restricted to the bus repeater (br) mode. figure 5. iqx output driver and pull-up current 1.2.2 pin and array side trickle current n-channel devices are used as a trickle current source (nominally 10 a) on the pin side and array side for each i/o port. upon reset, these current sources are turned on. they can be turned off by configuring the i/o port. 1.2.3 i/o port functional mode table 1 describes the various modes of the i/o port and the specification used by the i-cube development system software for proper bit stream generation. legend: ax -switch matrix signal px -i/o port signal ie -input enable oe -output enable clk -clock cke - clock enable column (bit) address decoder row (word) address decoder i/o port buffers i/o port buffers ra 0 ra 1 ra m-1 ca 0 ca 1 ca m-1 row (word) address column (bit) address p i p j (j, i) (i, j) i/o port br clk cke ie oe reg lat reg e e e e delay e lat switch matrix ck ck nc nc pu pd a)pull down b)normal pull up c)additional weak pullup d)additional strong pullup d c a b v dd .pad i/o port
iqx family data sheet february 2001 revision 6.2 11 symbol i/o port function mnemonic input - the external signal is buffered from the i/o port pin to the corresponding switch matrix line. in this mode an optional input enable (ie) can be selected. either polarity can be selected for ie. the default level is a logic 1. in registered input ( with variable length shift register and inversion) - the external signal at the i/o port pin is registered into a 7-bit edge-triggered shift register within the i/o port. an 8-to-1 mux selects either the input (bit 0) or one of the 7 output bits of the shift register and connects it to the corresponding signal line in the switch matrix through a register. any tap on the shift register can be selected. the true or complement of the incoming signal can be selected. the default is bit 0, true value. a clock source is required in this mode. either edge of clk can be selected. the default for clk is rising edge. a clock enable (cke) and input enable (ie) are also available but not required. either polarity can be selected for ie and cke. the default level for ie and cke is a logic 1. the outputs of the shift register are unknown after hardware reset (trst* = 0). ri& [bit = value]& [inv = value] latched input - the external signal at the i/o port pin is latched by a level-sensitive flip-flop within the i/o port. a latch enable source is required in this mode. the latch enable source is composed of clk and cke, and at least one must be specified. an input enable (ie) is also available but not required. either polarity can be selected for clk, cke and ie. the default level for all three is a logic 1. the output of the flip-flop is unknown after hardware reset (trst* = 0). li output - the internal signal is buffered from the corresponding switch matrix line to the i/o port pin. in this mode an optional output enable (oe ) can be selected. either polarity can be selected for oe. the default level is a logic 0. op latched output - the internal signal on the switch matrix line is latched by a level-sensitive flip-flop within the i/o port. a latch enable source is required in this mode. the latch enable source is composed of clk and cke, and at least one must be specified. an output enable (oe ) is also available but not required. either polarity can be selected for clk and cke. the default level for both is a logic 1. either polarity can be selected for oe . the default level is a logic 0. the output of the flip-flop is unknown after hardware reset (trst* = 0). lo registered output - the internal signal on the switch matrix line is registered by an edge- triggered flip-flop within the i/o port. a clock source is required in this mode. either edge of clk can be selected. the default for clk is rising edge. a clock enable (cke) and output enable (oe ) are also available but not required. either polarity can be selected for cke and oe . the default level for cke is a logic 1 and the default level for oe is a logic 0. the output of the flip-flop is unknown after hardware reset (trst* = 0). ro bidirectional transceiver - in this mode, the i/o buffer acts as a bidirectional transceiver between the i/o port pin and the corresponding switch matrix line. this mode requires an input enable (ie) and output enable (oe ). either polarity can be selected for each but the default level for ie is a logic 1 and the default level for oe is a logic 0. when the same source (with default polarities) is used for ie and oe , it effectively acts as direction control. when the same control signal (with one polarity inverted) is used for ie and oe , it effectively acts as a bus repeater (br) (see below) when both are enabled, and as no connect (nc) when neither is enabled. bt table 1. summary of programmable i/o attributes for iqx devices px ax ie cke px ax clk 7 dq 0 0 1 ce 07 ie d le q cke clk px ax ie px ax oe d le q cke clk px ax oe d ce q cke clk px ax oe px ax ie oe
iqx family data sheet 12 revision 6.2 february 2001 bidirectional transceiver with latched input - this mode combines latched input (li) and output buffer (op). a latch enable source is required in this mode. the latch enable source is composed of clk and cke, and at least one must be specified. either polarity can be selected for clk and cke. the default level for both is a logic 1. this mode also requires an input enable (ie) and output enable (oe ). either polarity can be selected for ie and oe . the default level for ie is a logic 1 and the default level for oe is a logic 0. the output of the flip-flop is unknown after hardware reset (trst* = 0). bt&li bidirectional transceiver with registered input - this mode combines registered input with programmable tap and inversion (ri) and buffered output (op). a clock source is required in this mode. either edge of clk can be selected. the default for clk is rising edge. a clock enable (cke) is available but not required. either polarity can be selected. the default level for cke is a logic 1. this mode also requires an input enable (ie) and output enable (oe ). either polarity can be selected for each. the default level for ie is a logic 1 and the default level for oe is a logic 0. the output of the flip-flop is unknown after hardware reset (trst* = 0). bt&ri& [bit = value]& [inv = value] bidirectional transceiver with latched output - this mode combines latched output (lo) and input buffer (in). a latch enable source is required in this mode. the latch enable source is composed of clk and cke. at least one must be specified. either polarity can be selected for clk and cke. the default level for both is a logic 1. this mode also requires an input enable (ie) and output enable (oe ). either polarity can be selected for ie and oe . the default level for ie is a logic 1 and the default level for oe is a logic 0. the output of the flip-flop is unknown after hardware reset (trst* = 0). bt&lo bidirectional transceiver with registered output - this mode combines registered output (ro) and buffered input (in). a clock source is required in this mode. either edge of clk can be selected although the default is rising edge. a clock enable (cke) is available but not required. either polarity can be selected but the default level is a logic 1. this mode also requires an input enable (ie) and output enable (oe ). either polarity can be selected for ie and oe . the default level for ie is a logic 1 and the default level for oe is a logic 0. the output of the flip-flop is unknown after hardware reset (trst* = 0). bt&ro bidirectional transceiver with registered i/o - this mode is a combination of registered input (ri) with programmable tap and inversion, and registered output (ro). a clock source is required in this mode. either edge of clk can be selected. the default is rising edge. a clock enable (cke) is available but not required. either polarity can be selected for cke. the default level is a logic 1. this mode also requires an input enable (ie) and output enable (oe ). either polarity can be selected for ie and oe . the default level for ie is a logic 1 and the default level for oe is a logic 0. the output of the flip-flops is unknown after hardware reset (trst* = 0). bt&ri& [bit = value]& [inv = value] &ro other bt modes - other combinations of i/o port modes (not covered in this table) are less likely but can be used. the mnemonic is bt [&ri | &li] [&ro | &lo], where the specification inside the brackets ? [ ] ? is optional and ? | ? stands for either or. insure that control signal requirements are met. in these modes, the output of the flip-flops is unknown after hardware reset (trst* = 0). symbol i/o port function mnemonic table 1. summary of programmable i/o attributes for iqx devices (continued) d le q cke clk ie px ax oe px ax oe cke clk 7 dq 0 0 1 ce 07 ie d le q cke clk px ax ie oe px ax ie oe ce cke clk dq d i ce q o q i d o px ax ie oe cke clk 7 0 0 1 07
iqx family data sheet february 2001 revision 6.2 13 bus repeater - in the bus repeater mode, the i/o port behaves as a wire (with a non-zero propagation delay). this unique feature patented by i-cube incorporates a self-sensing circuit to determine signal direction and does not require a direction control signal. when multiple i/o ports, configured as ? bus repeater ? , are connected together through the switch matrix to form a single internal node, an (open collector or tristatable) external signal appearing at any one of the i/o ports gets repeated (or broadcast) to other i/o ports. the bus repeater mode requires a pull-up current source (see section on ? programmable pull-up current ? ) to operate properly. for more details, refer to the technical note: ? the bus repeater mode. ? br array side force 0 - in this input mode, the switch matrix line is forced low (logic 0), regardless of the signal on the corresponding i/o port. in this mode an optional input enable (ie) can be selected. either polarity can be selected for ie. the default level is a logic 1. a0 array side force 1 - in this input mode, the switch matrix line is forced high (logic 1), regardless of the signal on the corresponding i/o port. in this mode an optional input enable (ie) can be selected. either polarity can be selected for ie. the default level is a logic 1. a1 pin side force 0 - in this output mode, the i/o port pin is forced low (logic 0), regardless of the signal on the corresponding switch matrix line. in this mode an optional output enable (oe ) can be selected. either polarity can be selected for oe . the default level is a logic 0. f0 pin side force 1 - in this output mode, the i/o port pin is forced high (logic 1), regardless of the signal on the corresponding switch matrix line. in this mode an optional output enable (oe ) can be selected. either polarity can be selected for oe . the default level is a logic 0. f1 no connect - in this mode, the i/o port pin is isolated from the switch matrix. this is done by tristating both the input and output part of the i/o buffer. nc symbol i/o port function mnemonic table 1. summary of programmable i/o attributes for iqx devices (continued) px ax px ax px ax px ax px ax px ax
iqx family data sheet 14 revision 6.2 february 2001 1.3 i/o control signals the iqx family has a structure that gives the user a lot of flexibility in controlling the behavior of each i/o port. as shown in figure 6 and described below, clock (clk), clock enable (cke), input enable (ie) and output enable (oe ) signals for each i/o port can be selected from multiple sources. the control polarity can also be individually selected. figure 6. i/o control gc0-gc12 13 = programming bits included in each i/o ports from mode control register 0-12 13 14 15 0 1 cke x seg 3 0-12 13 14 15 0 1 ie x seg 0 0-12 13 14 15 0 1 oe x seg 1 0-12 13 14 15 0 1 clk x seg 2 c o m p a r e 5-bit tag match = 1 5 = external pins seg 4 gt0-gt12 13 common to all i/o ports counter 5-bit terminal count 5 0 1 kclk kcke krst kclr k0/kclk k1/kcke k2/krst k3/kclr k4/k1f 1 0 port x+1 port x 5 count k0-k4 5 iob x-1 gc bus gt bus key bus 5 iob x iob x+1 1 1111
iqx family data sheet february 2001 revision 6.2 15 1.3.1 clock control an i/o port can be individually programmed to select its clock (clk) and clock enable (cke) signals from sixteen sources. the source can either be the two (four for iqx320 only) dedicated pins - gc0 and gc1 (gc0 through gc3 for iqx320), 11 (9 for iqx320) clock pins that are shared with signal i/o pins - gc2 through gc12 (gc4 through gc12 for iqx320), the nearest neighboring i/o port, or the match signal generated using key control (k0 - k4) pins. 1.3.2 tristate control an i/o port can be individually programmed to select its input enable (ie) and output enable (oe ) signals from sixteen signals. the source can either be the four (five for iqx320 only) dedicated tristate pins - gt0 through gt3 (gt0 through gt4 for iqx320), nine (eight for iqx320) tristate pins that are shared with signal i/o pins - gt4 through gt12 (gt5 through gt12 for iqx320), the nearest neighboring i/o port, or the match signal generated using key control (k0 - k4) pins. 1.3.3 neighboring i/o port as a control source a physically adjacent i/o port on the die can be used as a source for any of the i/o control signals. port 1 is the control source for port 0, port 2 is the control source for port 1 and so on. port 0 is the control source for the highest number i/o port on the device die . note that due to bondout restrictions the neighboring i/o port may not always be brought out to a package pin on the iqx240b and iqx128b devices. 1.3.4 key control pins as a control source the key control feature on the iqx devices allows the user to encode mutually exclusive control signals for use as i/o control signals. the key pins, k0 through k4 are shared with i/o ports. this feature, shown schematically in figure 6, works as follows: each i/o port contains a 5-bit tag which can be programmed with a unique value when the i/o ports are configured. a comparator in each i/o port continuously compares the programmed tag value with the signals present on the key pins or the output of the internal 5-bit counter. the output of the comparator, which produces a logic 1 on a match, can be selected as a control signal. the key control is intended for use with level sensitive signals such as ie, oe , cke (in registered modes only). if key control is used in situations where a short glitch on the internal ? match ? signal is unacceptable (i.e., using the key port for clk in registered modes and clk and/or cke in latched modes), it is recommended that one of the key pins be used as a qualifier and its value changed after the other key pins have stabilized to prevent glitches on the internal ? match ? signal. note that when key match is used as output enable (oe ) the match will disable the driver, while a non-match will enable it. this can be reversed by configuring the i/o port to use reverse polarity for oe . depending on the value of the counter enable bit in the mode control register (see table 10, the key input to the 5-bit comparator comes either directly from the key pins (k0 through k4) or from the output of an internal 5-bit up counter. if the counter is selected by setting the counter enable bit to a logic 1, the key pins serve as control inputs to the counter as described below. k0/kclk - counter clock input k1/kcke - counter clock enable k2/krst - counter (synchronous) reset k3/kclr - counter (asynchronous) clear k4/k1f - counter select ? 1f ? hex the counter is a 5-bit modulo up counter controlled by the rising edge on the counter clock pin (kclk). it counts up to the 5-bit value programmed in the mode control register and then resets to zero on the following clock edge. kcke pin is used to qualify the clock. clocking is enabled when kcke is high and disabled when low. when the k1f pin is asserted (high), the output of the counter is forced to ? 11111 ? regardless of the internal count. during this time the counter continues to count up in response to the clock input. when the krst pin is asserted, the counter is reset on the following clock edge. kclr on the other hand is an asynchronous clear. when asserted, the counter is immediately reset to zero. when the device is reset, the counter enable bit and the five count value bits are reset to zero. 1.3.5 default values for control signals when the device is reset all i/o ports are set to the default configuration of flow-through input (in), this is achieved by setting the 16-to-1 muxes shown in figure 6, to select input 15 (v ss ); while the 2-to-1 muxes used for polarity selections are set to select non-inverted value for clock (clk) and clock enable (cke), and inverted value for input enable (ie) and output enable (oe ). 1.4 rapidconfigure (rc) interface the rapidconfigure (rc) interface allows switch matrix connections and i/o port configurations to be changed quickly. a single switch matrix connection can be made or broken in a single rapidconfigure cycle; while a single i/o port or group of
iqx family data sheet 16 revision 6.2 february 2001 2, 4, 8 or 16 i/o ports (having the same configuration) can be configured in a minimum of one or maximum of eight rapidconfigure cycles. the rapidconfigure interface shown in figure 7 is a write only interface. its operation is some what similar to a memory write cycle in a microprocessor system - it uses address, data and control signals to write to the switch matrix sram cells and i/o port configuration registers. the control bus, {p/ s (port/switch ) , c[1:0]} defines the type of operation performed by the rapidconfigure cycle, while the row address, ra[m-1:0], and column address, ca[m-1:0], provide the necessary addresses and/or data for the different operations. the value ? m ? is different for different devices as shown in table 2. we (write enable) acts as chip select while strobe is the write strobe. notes: 1. the iq compatibility mode uses the lower of the two numbers shown. 2. due to the requirements for compatibility with the iq family and/or bondout restrictions, this number is lower than (# in row 1 - # in row 2) for some devices. figure 7. iqx rapidconfigure system interface in a typical system, an embedded processor will compute the required row address, column address and control values and apply them to the iqx device. alternatively, these values could be computed before hand using the i-cube supplied development system software (ids100), and stored in a lookup table. the rapidconfigure mode is enabled or disabled by correctly setting the rc bit in the mode control register. table 3 shows the different rapidconfigure options, depending on the values of the ? rc ? and ? rm ? bits in the mode control register. during hardware reset (trst* = 0) these bits are set to the signal value on the ? rce ? (rapidconnect enable) pin . the values of these bits can then be changed if required using the jtag serial interface. note that the ? p/ s ? signal shown in figure 7 is required only if the rapidconfigure interface is used for changing i/o port configuration, i.e., when rc bit = 1 and rm bit = 1. the pin is available for use as signal i/o pin (i/o port) when rm bit = 0. table 8 summarizes the different options. compatibility with the iq family devices is achieved by connecting the rce pin to v ss on the board. the user must ensure that the i/o ports used for the rapidconfigure interface are in the input (in) mode and any connections to corresponding signal lines in the switch matrix are cleared before attempting to configure the device using this interface. during device reset, the i/o ports used for the rapidconfigure interface are set to the required input (in) and all connections in the switch matrix are cleared. 1.4.1 switch matrix connection changes as indicated earlier, the switch matrix sram cells that control the connections among i/o ports form a two dimensional array. every sram cell location in the switch matrix that is being written to is uniquely identified by its row (or word) address and column (or bit) address. the real sram cell responsible for the connection between two i/o port numbers ? i ? and ? j ? on the feature iqx320 iqx240b iqx160 iqx128b total number of i/o ports 320 240 160 128 i/o ports used for rc interface 1 23 / 22 23 / 22 21/20 19/18 row address and column address bus widths 9987 i/o ports whose connections can be changed using rc interface 2 298 218 140 102 table 2. rapidconfigure interface pin count cpu address bus config control logic i/o port c 0 c 1 we strobe clk data bus iqx i/o port p/s i/o port optional ra[m-1:0] rce ca[m-1:0] tdi tms tck trst* rc bit rm bit operation 0 0 rapidconfigure mode is disabled. the device can only be configured using the jtag-based serial interface. in this mode, the i/o ports used for rapidconfigure interface can be used for as signal i/o ports. 1 0 rapidconfigure mode is enabled for changing switch matrix connections but not for i/o port configuration. the i/o ports can only be configured using the jtag-based serial interface. in this mode, the signal coming from the p/s pin is forced low internally. the p/s pin is available as a signal i/o port. 1 1 rapidconfigure mode is enabled for changing switch matrix connections and i/o port configurations. table 3. rapidconfigure options
iqx family data sheet february 2001 revision 6.2 17 device die has the row address of binary (i) and column address of binary (j), or vice versa. furthermore, when dealing with the bondout devices iqx240b and iqx128b the i/o port numbers on the device package must first be mapped to the i/o port number on the device die to determine the row and column address of the real sram cell. refer to appendix a for the tables and decision logic used to determine the location of the real sram cell, and the mapping of i/o port numbers on the device package to i/o port numbers on the device die. the control bus, {p/ s =0, c[1:0]} specifies the type of connection change, either make or break; the row and column addresses are the values corresponding to the two i/o port numbers as determined using the tables in appendix a. p/ s is set to 0 when changing switch matrix connections using rapidconfigure. as indicated in table 4, when the control bit c1 is held low during a make or break operation, the remaining sram cells belonging to the word addressed by the row address are automatically cleared. this feature can be used to speed up connection changes as described below. in one common crossbar application, the signal i/o ports on the device are divided into equal groups of inputs and outputs, and a pin in the output group is required to be connected to any pin in the input group. by judicious assignment of the i/o ports to the output group, one can ensure that for every output port, the real sram cells controlling the connection between that output port and all ports in the input group fall on the word corresponding to the output port number. with this assignment, when establishing a new connection using rapidconfigure, any existing connection to that output i/o port is automatically broken (c1=0). thus a connection change, i.e., breaking an existing connection and then making a new one, can be accomplished in one rapidconfigure cycle. tables in appendix a provide information on determining the word locations of real sram cells. refer to i- cube ? s application notes for further details of using rapidconfigure. attempting to alter the contents of the sram cells responsible for connections to the i/o ports used for the rapidconfigure interface will result in unpredictable results. notes: (1) binary (j) is the m-bit binary equivalent value of i. right most bit is lsb. m equals row/column address width. ? i ? and ? j ? refer to the i/o port number on the device die. (2) ? r ? is the i/o port number on the die corresponding the highest available signal i/o port. (3) assumes the real sram cell controlling the connection has row address=binary(j) operation control bus {p/s , c[1:0]} row address ra[m-1:0] column address ca[m-1:0] break the connection between i/o ports i & j by writing a ? 0 ? to the sram cell location whose row address is i and column address is j, [0 i, j r]. other sram cells are unchanged, i.e., no other connections are affected. (2,3) 010 binary(i) binary(j) make the connection between i/o ports i & j by writing a ? 1 ? to the sram cell location whose row address is i and column address is j, [0 i, j r]. other sram cell are unchanged, i.e., no other connections are affected. (2,3) 011 binary(i) binary(j) break the connection between i/o ports i & j by writing a ? 0 ? to the sram cell location whose row address is i and column address is j, [0 i, j r]. clear all sram cells on row i; i.e., break all the connections controlled by the real sram cells belonging to row i. (2,3) 000 binary(i) binary(j) make the connection between i/o ports i & j by writing a ? 1 ? to the sram cell location whose row address is i and column address is j, [0 i, j r]. clear all sram cells on row i; i.e., break all the connections controlled by the real sram cells belonging to row i. (2,3) 001 binary(i) binary(j) table 4. changing switch matrix connections using rapidconfigure
iqx family data sheet 18 revision 6.2 february 2001 1.4.2 i/o port configuration configuring i/o ports using the rapidconfigure interface involves two steps. during the first step the 50-bit i/o port configuration holding register, consisting of seven 8-bit segments, is loaded with the configuration data. the loading is accomplished one 8-bit segment at a time, and may take up to 7 rapidconfigure cycles to load this register. in the second step, the data in the i/o port configuration holding register is completely transferred to the individual i/o ports in a single rapidconnect cycle. a single i/o port, or a group of 2, 4, 8 or 16 contiguous i/o ports with a starting address of modulo 2, 4, 8 or 16 respectively, (and requiring the same configuration) can be configured in a single rapidconfigure cycle during this step. when using rapidconfigure for configuring i/o ports, the control bus, {p/s = 1, c[1:0]} specifies the type of operation; and the row and column addresses provide the information about the i/o port, or the group of ports to be configured. p/s is set to 1 when configuring i/o ports using rapidconfigure. refer to table 5 for details. the i/o port information specified in the row and column address values applies to the i/o pad location on the die . when using the rapidconfigure interface for configuring bondout versions such as the iqx240b and iqx128b proper translation for i/o port number on the package to the corresponding i/o port number on the die must first be made. refer to appendix a for the mapping. i/o ports used for the rapidconfigure interface p/ s , c[1:0], ra, ca, we and strobe , cannot be configured using the rapidconfigure interface. combinations not listed in table 5 may result in unpredictable results and should be avoided. notes: (1) ? sss ? is the 8-bit segment in the 50-bit i/o port configuration holding register and dddddddd is the 8-bit data to be loaded. right most bits are lsbs. (2) ? ppppp.... ? is the i/o port or i/o port group number to be configured. this vector is 9-bits long or less, depending on the device and siz e of the i/o port group. the i/o port group is a contiguous group of i/o ports with the lowest i/o port number being (ppppp....) multipl ied by (number of ports in the group). (3) ? r ? is the i/o port number on the die corresponding to the highest i/o port number on the package that can be configured using rap idconfigure. 1.4.3 i/o port configuration holding register i/o port configuration holding register is used to hold the data that is to be loaded into the i/o port configuration register. this 50-bit holding register consists of six 8-bit segments and one 2- bit segment, and is loaded one segment at a time using the rapidconfigure interface. using the rapidconfigure interface, the holding register is first loaded with 50 bits of data that defines the i/o port function. the data is then transferred into the i/o port configuration register(s), also using the rapidconfigure interface. depending on the current contents of the holding register segments, it may take 7 rapidconfigure cycles or less to load the holding register. the holding register contains unknown values when the device is reset. table 6 describes the i/o port programming bits and shows their location in the i/o port configuration holding register. table 7 shows the bit values for the various i/o port configurations. operation control bus {p/s , c[1:0]} iqx320, iqx240b iqx160 iqx128b row add. ra[8:0] col. add. ca[8:0] row add. ra[7:0] col. add. ca[7:0] row add. ra[6:0] col. add. ca[6:0] load configuration register (1) 110 000000sss 0dddddddd 0000sssd 0ddddddd 000sssd ddddddd configure port i [0 i r] (2,3) 111 ppppppppp 000000001 pppppppp 00000001 ppppppp 0000001 configure 2 i/o port group 111 pppppppp0 000000011 ppppppp0 00000011 pppppp0 0000011 configure 4 i/o port group 111 ppppppp00 000000111 pppppp00 00000111 ppppp00 0000111 configure 8 i/o port group 111 pppppp000 000001111 ppppp000 00001111 pppp000 0001111 configure 16 i/o port group 111 ppppp0000 000011111 pppp0000 00011111 ppp0000 0011111 table 5. configuring i/o ports using rapidconfigure interface
iqx family data sheet february 2001 revision 6.2 19 name seg# bit# group function reset value description ies0 0 0 input group 1 input enable (ie) source bit 0 (lsb). ies1 1 1 input enable (ie) source bit 1. ies2 2 1 input enable (ie) source bit 2. ies3 3 1 input enable (ie) source bit 3 (msb). inv_ie 4 1 invert polarity for input enable; default is active high. in 5 1 input port mode. a0 6 0 force array side low. a1 7 0 force array side high. oes0 1 0 output group 1 output enable (oe ) source bit 0 (lsb). oes1 1 1 output enable (oe ) source bit 1. oes2 2 1 output enable (oe ) source bit 2. oes3 3 1 output enable (oe ) source bit 3 (msb). inv_oe 4 1 invert polarity for output enable, default is active low. op 5 0 output port mode. f0 6 0 force pin side low. f1 7 0 force pin side high. clks0 2 0 clock source, register, and latch group 1 clock (clk) source bit 0 (lsb). clks1 1 1 clock (clk) source bit 1. clks2 2 1 clock (clk) source bit 2. clks3 3 1 clock (clk) source bit 3 (msb). lo 4 0 latched output mode. li 5 0 latched input mode. ro 6 0 registered output mode. ri 7 0 registered input mode. table 6. i/o port configuration bits
iqx family data sheet 20 revision 6.2 february 2001 ckes0 3 0 clock enable group 1 clock enable (cke) source bit 0 (lsb). ckes1 1 1 clock enable (cke) source bit 1. ckes2 2 1 clock enable (cke) source bit 2. ckes3 3 1 clock enable (cke) source bit 3 (msb). inv_cke 4 1 invert polarity for clock enable; default is enabled when high for register and transparent when high for latch. inv_clk 5 0 invert polarity for clock; default is rising edge triggered for register and transparent when high for latch. inv_pi 6 0 invert input data in registered input (ri) mode. reserved 7 0 reserved for internal use. must be set to default value. k0 4 0 key control and pipeline delay group 0 key tag bit 0 (lsb). k1 1 0 key tag bit 1. k2 2 0 key tag bit 2. k3 3 0 key tag bit 3. k4 4 0 key tag bit 4 (msb). delay0 5 0 input pipeline delay bit 0 (lsb). delay1 6 0 input pipeline delay bit 1. delay2 7 0 input pipeline delay bit 2 (msb). br 5 0 misc. group 0 bus repeater mode. ias 1 1 array side trickle current. ips 2 1 pin side trickle current. pu_wk 3 0 weak static pull up current. pu_sg 4 0 strong static pull up current. nb 5 0 non-buffered mode. reserved 6 1 reserved for internal use. must be set to default value. reserved 7 1 reserved for internal use. must be set to default value. reserved 6 0 test group 0 reserved for internal use. must be set to default value. reserved 1 0 reserved for internal use. must be set to default value. name seg# bit# group function reset value description table 6. i/o port configuration bits (continued)
iqx family data sheet february 2001 revision 6.2 21 1.4.4 i/o port configuration register contents note: * user defined value each programmable i/o port on the iqx device contains a 50-bit configuration register. the function of an i/o port is determined by the contents of its configuration register. table 7 shows the contents for the different i/o functions. combinations that are not listed are illegal and may result in improper operation or damage to the device. the bits in table 7 indicated by a ? * ? refer to the values and polarity of the various control sources and must be filled in correctly based on the user selection of the control sources. 1.4.5 reset commands the rapidconfigure interface can also be used to quickly clear the switch matrix and reset the i/o ports to their default state. refer to the table below for details. when rapidconfigure is used for resetting the i/o ports the contents of the configuration holding register are set to the default state shown in table 8, however the contents of the mode control register and the state of the jtag controller are not affected. i/o mode mnemonic seg 6 bit 76543210 seg 5 bit 76543210 seg 4 bit 76543210 seg 3 bit 76543210 seg 2 bit 76543210 seg 1 bit 76543210 seg 0 bit 76543210 . . . . . . . . . . nb pu_sq pu_wk ips ias br delay2 delay1 delay0 k4 k3 k2 k1 k0 . inv_pi inv_clk inv_cke ckes3 ckes2 ckes1 ckes0 ri ro li lo clks3 clks2 clks1 clks0 f1 f0 op inv_oe oes3 oes2 oes1 oes0 a1 a0 in inv_ie ies3 ies2 ies1 ies0 value after reset 00000000 11000110 00000000 00011111 00001111 00011111 00111111 input in 00000000 11000110 00000000 00011111 00001111 00011111 00111111 input w/ tristate 00000000 11000110 000***** 00011111 00001111 00011111 001***** latched input li 00000000 11000110 000***** 00****** 0010**** 00011111 00111111 latched input w/ tristate 00000000 11000110 000***** 00****** 0010**** 00011111 001***** registered input ri 00000000 11000110 ******** 0******* 1000**** 00011111 00011111 registered input w/ tristate 00000000 11000110 ******** 0******* 1000**** 00011111 000***** output op 00000000 11000110 00000000 00011111 00001111 00101111 00001111 output w/ tristate 00000000 11000110 000***** 00011111 00001111 001***** 00001111 latched output lo 00000000 11000110 000***** 00****** 0001**** 00101111 00001111 latched output w/ tristate 00000000 11000110 000***** 00****** 0001**** 001***** 00001111 registered output ro 00000000 11000110 00000000 00****** 0100**** 00001111 00001111 registered output w/ tristate 00000000 11000110 000***** 00****** 0100**** 000***** 00001111 bidirectional transceiver bt 00000000 11000110 00000000 00111111 00001111 001***** 001***** bidirectional transceiver w/ latched input bt&li 00000000 11000110 000***** 00****** 0010**** 001***** 001***** bidirectional transceiver w/ registered input bt&ri 00000000 11000110 000***** 00****** 1000**** 001***** 000***** bidirectional transceiver w/ latched output bt&lo 00000000 11000110 000***** 00****** 0001**** 001***** 001***** bidirectional transceiver w/ registered output bt&ro 00000000 11000110 000***** 00****** 0100**** 000***** 001***** pin force 0 f0 00000000 11000110 00000000 00011111 00001111 01001111 00001111 pin force 1 f1 00000000 11000110 00000000 00011111 00001111 10001111 00001111 array force 0 a0 00000000 11000110 00000000 00011111 00001111 00011111 01011111 array force 1 a1 00000000 11000110 00000000 00011111 00001111 00011111 10011111 bus repeater br 00000000 110**111 00000000 00011111 00001111 00101111 00111111 no connect nc 00000000 11000110 00000000 00011111 00001111 00011111 00001111 table 7. i/o configuration register contents
iqx family data sheet 22 revision 6.2 february 2001 1.5 jtag-based configuration controller in the iqx devices, the i/o attributes and switch matrix connections can be programmed using the jtag serial bus. additionally, the rapidconfigure interface, used for quickly changing i/o port configurations and switch matrix connections, can be enabled or disabled using the jtag serial bus. the jtag-based serial mode is always available for configuration regardless of whether the rapidconfigure mode is enabled or disabled. however proper care must be taken when switching between jtag and rapidconfigure for configuring the devices. the user must ensure that the rapidconfigure mode is first disabled by using jtag serial mode to set the rc bit to zero in the mode control register before attempting to change switch matrix connections or i/o port configuration through jtag. in most cases, the user does not need to know the details of the jtag protocol. the i-cube supplied software will automatically generate the necessary bit stream from a higher-level textual description of the required configuration. 1.5.1 jtag interface the jtag interface is a serial interface and uses five pins: test data in (tdi), test data out (tdo), test clock (tck), test mode select (tms) and test reset (trst*). tck is used to clock data in and out of tdi and tdo. tms, in conjunction with tdi implements a state machine that controls the various operations of the jtag protocol. data on the tdi and tms pins is clocked into the iqx device on the rising edge of the tck signal, while the valid data appears on the tdo pin after the falling edge of tck. on the iqx devices, trst* is used to reset both the device and the jtag controller. 1.5.2 i/o port configuration i/o port configuration is accomplished by loading the appropriate bit stream into the programming registers present at each i/o port. the jtag serial bus is used to load configuration data into the i/o port programming registers, one i/o port at a time. 1.5.3 switch matrix configuration the contents of the sram cells controlling switch matrix connections can be modified using the jtag. this is accomplished by loading the configuration data, one word at a time into the sram cells in the switch matrix. 1.5.4 mode control register configuration the iqx device contains a mode control register. some bits in the register are used to store user flags such as rapidconfigure enable, and certain non-user flags required for proper functioning of the device. the contents of this register can be changed using the jtag interface. refer to table 10 for details. iqx320, iqx240b iqx160 iqx128b operation control bus (p/s, c[1:0]) row add. ra[8:0] col. add. ca [8:0] row add. ra[7:0] col. add. ca[7:0] row add. ra[6:0] col. add. ca[6:0] clear all switch matrix sram cells (break connections) 111 000000000 000100000 00000000 00100000 0000000 0100000 clear all switch matrix sram cells (break connections) and set all i/o ports to power-on default function [input (in)] 111 000000000 001100000 00000000 01100000 0000000 1100000 table 8. rapidconfigure reset commands
iqx family data sheet february 2001 revision 6.2 23 2.0 m iscellaneous d etails 2.1 device reset to ensure proper operation, the device reset pin, trst* must be held low during power up. the reset pulse must be at least 200 ns long. the iqx device is ready for configuration as soon as it comes out of reset. the recommended reset circuitry is shown in figure 8, using an external supervisor device. . figure 8. reset circuit it should be noted that the trst* pin must not be driven by any devices which cannot guarantee a low signal during power-up. improper devices are those whose pins are either high or tri- stated during power-up. examples of such devices are sram- based fpgas. when the device is in operation, different functional blocks can be reset using one of following methods. each method performs a slightly different action as shown in table 9. in any of the reset methods the edge and level-sensitive flip- flops in the i/o port buffers are not cleared and will have unknown output values. 2.2 mixed voltage operation there are multiple sources for power on the iqx device. the first one called v dd is a 5v source and is used to power the device core, including the switch matrix sram cells, i/o port logic (excluding the i/o buffer driver), i/o control logic, jtag logic and other circuitry. the i/o buffer drivers are powered by a different source called v dd .pad. the number of v dd .pad sources depends on the device. table 13 shows the number of v dd .pad sources and the i/o ports controlled by them. the v dd .pad pins can be connected to either a 5v or 3v supply. this makes it easy to interface iqx device to 5v and/or 3v logic levels. 2.3 power pin v dd .x the iqx devices contain a pin marked v dd .x. the devices contain an on-chip charge pump. in order for the charge pump to operate correctly, it is required that the v dd.x pin be left floating and completely unconnected. the charge pump should also be left in its default ? on ? setting. this is controlled by bit #6 (c_pump) of the mode control register. vdd ref gnd rst rst pbrst iqx supervisor +5 vmon trst* reset method switch matrix i/o ports i/o config. holding register jtag state machine rapidconfigure interface pulsing trst* low cleared set to input (in) set to input (in) reset enabled if rce pin = 1 shifting in the ? device reset ? instruction using jtag cleared set to input (in) set to input (in) unchanged enabled if rce pin = 1 applying ? i/o port and switch matrix reset ? instruction using rapidconfigure interface cleared set to input (in) set to input (in) unchanged stays enabled applying ? switch matrix reset ? instruction using rapidconfigure interface cleared unchanged unchanged unchanged stays enabled table 9. device reset
iqx family data sheet 24 revision 6.2 february 2001 2.4 mode control register the iqx device contains a 16-bit mode control register. it stores the rapidconfigure enable and certain other non-user flags which must be set correctly for the proper functioning of the device. table 10 shows the bit assignment and their function. a special jtag instruction is used to write to the mode control register. when this register is written using jtag the least significant bit (bit 0) is shifted in first. bit # name default description 0 kcnt 0 key counter enable. when set, uses the internal 5-bit counter to provide key address 1 rm * used to enable iob configuration through rapidconfigure interface. default value equals the rce pin value on reset. 2 rc * enables or disables rapidconfigure mode. default value equals the rce pin value on reset. 3 iob_pu1 1 iob pull up 10k ref 4 bro_pw1 1 br external one-shot pulse width 10k ref 5 bri_pw1 1 br internal one-shot pulse width 10k ref 6 c_pump 1 charge pump enable bit 7 iob_pu2 0 iob pull up 20k ref 8 bro_pw2 0 br external one-shot pulse width 20k ref 9 bri_pw2 0 br internal one-shot pulse width 20k ref 10 internal 0 for internal use. should not be changed by the user. 11 kval0 0 terminal count value bit 0 (lsb) when internal counter is used as key address 12 kval1 0 terminal count value bit 1 when internal counter is used as key address 13 kval2 0 terminal count value bit 2 when internal counter is used as key address 14 kval3 0 terminal count value bit 3 when internal counter is used as key address 15 kval4 0 terminal count value bit 4 (msb) when internal counter is used as key address table 10. mode control register bit assignment
iqx family data sheet february 2001 revision 6.2 25 3.0 i n s ystem c onfiguration u sing jtag- based c onfiguration c ontroller the jtag-based configuration mode allows the user to initialize the device, configure the i/o ports, establish connections through the switch matrix and set the contents of the mode control register. configuring the device using jtag involves two steps. in the first step the user generates the bit stream. two different software options - off-line and embedded bit stream generation - are available to accomplish this task. the choice depends on the target application. the second step is the actual downloading of the bit stream into the device. the downloading circuitry can take on different forms, depending on the target application. figure 9. off-line bit stream generation figure 10. embedded bit stream generation 3.1 bit stream generation the configuration bit stream can be generated off-line or in- system by an embedded cpu using one of the following methods: by using i-cube development system software product ids100. by user written code based on the information provided in the ? iqx family register programming users reference. ? if the bit stream is generated off-line then, depending on the application, it is either stored in non-volatile memory or directly downloaded from a host processor such as a pc connected to the target hardware. the software used for off-line generation accepts a text file describing the desired configuration - connections between different i/o ports, functional attributes of each i/o port, and settings of certain user flags - and generates a file containing the bit stream. 3.2 bit stream downloading the bit stream can be downloaded into the iqx device using several different hardware schemes. the choice depends on the end application. all these schemes use the standard jtag protocol and timing. as per the jtag protocol, the clock signal (tck) must be supplied externally. if the target hardware is controlled by a computer such as a pc, the parallel port on the computer can be used to download the bit stream. i-cube provides a software utility to perform the downloading. under this scheme, the necessary data for tdi and tms pins as well as the (software generated) tck clock signal are sent over the parallel port. an on-board byte-wide eprom or e 2 prom, or a serial e 2 prom can be used to store the bit stream. using minimal external logic, the bit stream stored in one of these devices can be downloaded into the iqx device(s) over the tdi and tms pins, with the tck pin used for synchronization. the clock signal for the tck pin is generated by the external logic. if the target system has an on-board microcontroller, the bit stream data can be read from memory and downloaded into the iqx device(s) using 3 i/o pins on the microcontroller to generate the required tdi, tms and tck signals. for real-time applications, the microcontroller/microprocessor can generate the bit stream (using the i-cube supplied software examples or user written code) and then download it into the iqx device in a single operation. create configuration file (text file) compile configuration file to create configuration bitstream convert bitstream for use with configuration circuitry in the target system serial eprom eprom onboard microcontroller download cable memory configuration circuitry iqx application software iqx programming library
iqx family data sheet 26 revision 6.2 february 2001 the actual time required to download the configuration bit stream and program a iqx device depends on the device(s) used, the user ? s specific configuration pattern, and jtag clock frequency. table 11 shows the number of jtag cycles and configuration time required for some typical operations. the size of the memory (number of bytes) required is two (one each for tdi and tms) times the number of jtag cycles divided by eight. 3.3 configuring multiple iqx devices the jtag-based controller allows a single device or multiple iqx devices connected in a chain to be configured in a single operation. for multiple device configuration, the pins are connected as shown in figure 11. figure 11. configuring multiple iqx devices during the initial configuration sequence, the internal controllers on all iqx devices are first brought to their reset state by pulsing the trst* reset pin low. this is followed by the actual configuration bit stream, which is downloaded into the iqx devices over the tdi and tms pins. tdi iqx iqx iqx u3 u2 u1 tdo tck tms trst* tdi tck tms trst* tdo tdi tck tms trst* tdo tdi tck tms trst* tdo operation iqx320 iqx240b iqx160 iqx128b jtag cycles config. time bitstream size jtag cycles config. time bitstream size jtag cycles config. time bitstream size jtag cycles config. time bitstream size jtag reset sequence (tms = ? 11111 ? ) 5 500 ns 10 bits 5 500 ns 10 bits 5 500 ns 10 bits 5 500 ns 10 bits enable or disable rapid configure 42 4.2 s 84 bits 42 4.2 s 84 bits 42 4.2 s 84 bits 42 4.2 s 84 bits change iob attributes of one i/o port 76 7.6 s 152 bits 76 7.6 s 152 bits 76 7.6 s 152 bits 76 7.6 s 152 bits change iob attributes of all i/o ports 24 k 2.4 ms 6 kb 18 k 1.8 ms 4.5 kb 12 k 1.2 ms 4 kb 10 k 1.0 ms 2.5 kb reset jtag controller + reset all i/o ports + clear all sram cells 32 3.2 s 64 bits 32 3.2 s 64 bits 32 3.2 s 64 bits 32 3.2 s 64 bits connect or disconnect two i/o ports 346 34.6 s 692 bits 346 34.6 s 692 bits 186 18.6 s 372 bits 186 18.6 s 372 bits configure entire switch matrix 110 k 11.0 ms 27.5 kb 84 k 8.4 ms 21 kb 30 k 3.0 ms 7.5 kb 24 k 2.4 ms 6 kb completely configure the device (all i/o and all switch matrix connections) 134k 13.4 ms 34 kb 102 k 10.02 ms 26 kb 42 k 4.2 ms 11 kb 34 k 3.4 ms 9 kb table 11. number of jtag cycles and configuration time (using a 10 mhz jtag clock)
iqx family data sheet february 2001 revision 6.2 27 4.0 p in s ummary iqx320 iqx240b iqx160 iqx128b dir description p000 - p259, p262, p264, p266, p274, p276, p278, p280, p282, p284, p286, p288, p290, p292, p294, p305 p000 - p193, p225 p000 - p103, p107, p113, p118, p119, p123, p124, p129, p130, p135, p136 p000 - p083 i/o dedicated i/o ports p260, p261, p263, p265, p267 p194, p195, p196, p197, p198 p104, p105, p106, p108, p109 p84 -p88 i/o shared i/o ports i/o ports shared with general tristate control gt12 - gt8, used for input enable (ie) and output enable (oe ) signals. p268 - p272 p199 - p203 p110, p111, p112, p114, p115 p89 -p93 i/o shared i/o ports i/o ports shared with general clock control gc12 - gc8, used for clock (clk) and clock enable (cke) signals. p273, p275, p277, p279, p281 p204 - p208 p116, p117, p120, p121, p122 p94 -p98 i/o shared i/o ports i/o ports shared with key control k4 - k0, used for generating clock (clk), clock enable (cke), input enable (ie) and output enable (oe ) signals. p283, p285, p287, p289 p209-p212 p125-p128, p138, p137 p99-p102, p108, p107 i/o shared i/o ports i/o ports shared with general clock control gc7-gc4 for iqx320 and iqx240b and gc7- gc2 for remaining devices, used for clock (clk) and clock enable (cke) signals. p291, p293, p295 p213 - p215 p131 - p134 p103 - p106 i/o shared i/o ports i/o ports shared with general tristate control gt7 - gt5 for iqx320 and iqx240b and gt7 - gt4 for remaining devices, used for input enable (ie) and output enable (oe ) signals. gt4 - gt0 gt4 - gt0 gt3 - gt0 gt3 - gt0 i (dedicated) general tristate control pins used for input enable (ie) and output enable (oe ) signals. gc3 - gc0 gc3 - gc0 gc1 - gc0 gc1 - gc0 i (dedicated) general clock control pins used for clock (clk) and clock enable (cke) signals. p296 - p304 ca0 - ca8 p216 - p224 ca0 - ca8 p140 - p147 ca0 - ca7 p110 - p116 ca0 - ca6 i/o shared i/o ports i/o ports shared with column address (ca) bus p306 - p314 ra0 - ra8 p226 - p234 ra0 - ra8 p148 - p155 ra0 - ra7 p117 - p123 ra0 - ra6 i/o shared i/o ports i/o ports shared with row address (ra) bus p315 - p317 p235 - p237 p139, p156, p157 p109, p124, p125 i/o shared i/o ports i/o ports shared with p/s , c0 and c1 p318, p319 p238, p239 p158, p159 p126, p127 i/o shared i/o ports rapidconfigure write enable (we ) and write strobe (strobe ) trst* trst* trst* trst* i hardware reset device reset tdi, tms, tck, tdo tdi, tms, tck, tdo tdi, tms, tck, tdo tdi, tms, tck, tdo i i o jtag pins for downloading the serial configuration bitstream rce rce rce rce i rapidconfigure enable pin for enabling rapidconfigure interface after reset v dd .pad1 v dd .pad2 v dd .pad3 v dd .pad4 v dd .pad1 v dd .pad2 v dd .pad3 v dd .pad4 v dd .pad1 v dd .pad2 v dd .pad1 v dd .pad2 p p p p power & ground pins power pins for group 1 i/o buffer drivers. power pins for group 2 i/o buffer drivers. power pins for group 3 i/o buffer drivers. power pins for group 4 i/o buffer drivers. table 12. iqx pin summary
iqx family data sheet 28 revision 6.2 february 2001 v dd v dd .x v ss v dd v dd .x v ss v dd v dd .x v ss v dd v dd .x v ss p p p power pins for on-chip circuitry other than i/o buffer drivers. supply for switch matrix. ground pins. iqx320 iqx240b iqx160 iqx128b dir description table 12. iqx pin summary (continued) supply voltage pins powered by supply voltage iqx320 iqx240b iqx160 iqx128b v dd tdi,tms,tck,trst*, gc0-gc3, gt0-gt4 tdi,tms,tck,trst*, gc0-gc3, gt0-gt4 tdi,tms,tck, tdo, trst*, gc0, gc1, gt0-gt3 tdi,tms,tck,tdo,trst*, gc0, gc1, gt0-gt3 v dd .pad1 p000:p079, tdo p000:p059, tdo p000:p079 p000:p063 v dd .pad2 p080:p159 p060:p119 p080:p159 p064:p127 v dd .pad3 p160:p239 p120:p179 v dd .pad4 p240:p319 p180:p239 table 13. supply voltage source
iqx family data sheet february 2001 revision 6.2 29 5.0 e lectrical s pecifications 5.1 absolute maximum ratings (1) 5.2 recommended operating conditions 5.3 capacitance (3) notes: (1) exposure to absolute maximum rated conditions for extended periods may affect device reliability. (2) a maximum overshoot and undershoot of 2v for a maximum duration of 20 ns is acceptable. (3) capacitance measured at 25 c. sample-tested only. (4) v dd .pad1, v dd .pad2, v dd .pad3 and v dd .pad4 can operate at different voltages from each other. symbol parameter limits units v dd supply voltage to ground -0.3 to +7.0 v v dd .pad supply voltage for i/o buffer driver -0.3 to +7.0 v v in (2) input voltage -0.3 to (v dd .pad + 0.3) v t j junction temperature 150 c t stg storage temperature -65 to +150 c i os current per port pin 100 ma table 14. absolute maximum ratings symbol parameter limits units v dd supply voltage to ground 4.75 to 5.25 v v dd .pad (4) supply voltage for i/o buffer driver 4.75 to 5.25 2.97 to 3.63 v t a operating temperature 0 to 70 c table 15. recommended operating conditions symbol parameter min max units c in input capacitance (jtag pins) - 8 pf c out output capacitance (tdo pin) - 8 pf c port i/o signal port - 10 pf c cntl dedicated general clock and general tristate pin capacitance -10pf table 16. capacitance
iqx family data sheet 30 revision 6.2 february 2001 5.4 dc electrical specifications (t a = 0c to 70c, v dd = 5v5%; v dd .pad = 5v5%, or v dd .pad = 3.3v10%) notes: (1) these parameters are guaranteed but not tested in production. (2) no more than one output should be tested at a time and the duration of the test should be limited to less than one second. symbol parameter conditions iqx320, iqx240b iqx160, iqx128b unit min max min max v ih high-level input voltage 2.0 v dd + 0.3 2.0 v dd + 0.3 v v il low-level input voltage -0.3 0.8 -0.3 0.8 v v oh high-level output voltage v dd = min, v dd .pad = 4.75v i oh = - 8 ma 2.4 - 2.4 - v high-level output voltage v dd = min, v dd .pad = 2.97v i oh = - 4ma 2.4 - 2.4 - v v ol low-level output voltage v dd = min, v dd .pad = 4.75v i ol = 12 ma - 0.4 - 0.4 v low-level output voltage v dd = min, v dd .pad = 2.97v i ol = 12 ma - 0.4 - 0.4 v |i ih ? | ? |i il | input leakage current for i/o ports v dd = max, 0 v in v dd .pad - 5 - 5 a i pt i/o port trickling current (1) v dd = max, 0 v in v dd .pad - -25 - -25 a |i oz | tristate output off-state current v dd = max, 0 v in v dd .pad - 5 - 5 a i pu-wk programmed-weak additional pull-up current v dd = v dd .pad = 4.75v, v o = gnd 2.5 4.0 2.0 4.0 ma i pu-sg programmed-strong additional pull-up current v dd = v dd .pad = 4.75v, v o = gnd 9 13.5 8.0 13.5 ma i os short circuit current (1, 2) v dd = max, v o = gnd -60 - -60 - ma i ddq_core quiescent core power supply current v dd = max, i/o = gnd, cp = on - 85 - 85 ma v dd = max, i/o = gnd, cp = off - 8 - 8 ma i ddq_pad quiescent pad power supply current v dd .pad = 5.25v, all i/o = nc v dd = max, v o = gnd -80-80 a q ddd_core dynamic corepower supply current v dd .pad = 5.25v, v dd = max, no load, @ 1.0 mhz clock input, connect one output per input - 0.2 - 0.1 ma/ mhz q ddd_pad dynamic pad power supply current v dd .pad = 5.25v, v dd = max, no load, @ 1.0 mhz clock input, connect one output per input - 0.1 - 0.05 ma/ mhz table 17. dc electrical specifications
iqx family data sheet february 2001 revision 6.2 31 5.5 ac electrical specifications for iqx320 and iqx240b (t a = 0 c to 70 c, v dd = 5v5%; v dd .pad = 5v5%, or v dd .pad = 3.3v10%. assume two i/o ports connected through the switch matrix with 35 pf external loading) speed grade -10 -12 units ref. figure symbol parameter min max min max f rio register input/output, clock frequency (1, 2) 100 80 mhz t w-riol register input/output, clock pulse width, low (1, 2) 4.5 5.5 ns t w-rioh register input/output, clock pulse width, high (1, 2) 4.5 1000 5.5 1000 ns t s-rio register input/output, data setup time to clk 2.5 3.0 ns 13 t h-rio register input/output, clk to data hold time 2.0 2.0 ns t co-rio register input/output, clock to output data valid 9.5 11.5 ns f ri register input, clock frequency (1) 80 66 mhz t w-ril register input, clock pulse width, low 4.5 5.5 ns t w-rih register input, clock pulse width, high 4.5 1000 5.5 1000 ns t s-ri register input, data setup time to clk 2.5 3.0 ns 14 t h-ri register input, clk to data hold time 2.0 2.0 ns t co-ri register input, clock to output data valid 12.5 15.0 ns f ro register output, clock pulse frequency (1) 100 80 mhz t w-rol register output, clock width, low 4.5 5.5 ns t w-roh register output, clock width, high 4.5 1000 5.5 1000 ns t s-ro register output, data setup time to clk 4.5 5.0 ns 15 t h-ro register output, clk to data hold time 0.0 0.0 ns t co-ro register output, clock to output data valid 9.5 11.5 ns t phl , t plh one way signal propagation delay 10.0 12.5 ns t sk skew between output ports (1) 1.5 1.5 ns t w+ input flow through positive pulse width (2) 4.5 6.0 ns 16 t w- input flow through negative pulse width (2) 6.5 8.0 ns r data nrz data rate (1, 2) 180 150 mb/s t pzh-it , t pzl-it input enable (gt) to data valid 12.0 13.0 ns 17 t pzh-ot , t pzl-ot output enable (gt) to data valid 12.0 13.0 ns 18 t phz-ot , t plz-ot output enable (gt) to output at high z (1) 8.5 10.5 ns t w-li latch input, latch enable (gc) pulse width, low or high 4.5 5.5 ns t s-li latch input, data setup time to latch enable (gc) trailing edge 2.5 3.0 ns t h-li latch input, data to latch enable (gc) trailing edge hold time 2.0 2.0 ns 19 t co-li latch input, latch enable (gc) leading edge to data out delay 15.0 17.5 ns t p-lit latch input, transparent mode propagation delay 10.0 12.5 ns t w-lo latch output, latch enable (gc) pulse width, low or high 4.5 5.5 ns t s-lo latch output, data setup time to latch enable (gc) trailing edge 4.5 5.0 ns t h-lo latch output, data to latch enable (gc) trailing edge hold time 0.0 0.0 ns 20 t co-lo latch output, latch enable (gc) leading edge to data out delay 25.0 27.5 ns t p-lot latch output, transparent mode propagation delay 10.0 12.5 ns t kw-ri register input, minimum pulse width of key as clock enable, low or high 6.0 7.0 ns t ks-ri register input, clock enable (key) setup time to clk (gc) 3.0 3.5 ns 21 t kh-ri register input, clk (gc) to clock enable (key) hold time 2.0 2.0 ns t kco-ri register input, key clock to output data valid 13.0 15.5 ns table 18. ac electrical specifications for iqx320 and iqx240b
iqx family data sheet 32 revision 6.2 february 2001 notes: (1) these parameters are guaranteed but not tested in production. (2) the timing parameters are specified for a configuration where an input port is driving one output port. for configurations w here an input port is driving two or more output ports, the timing parameters are de-rated as shown in section 5.7 or table 20. these parameters are guaranteed but not tested in production. t kw-ro register output, minimum pulse width of key as clock enable, low or high 6.0 7.0 ns t ks-ro register output, clock enable (key) setup time to clk (gc) 5.0 5.5 ns 22 t kh-ro register output, clk (gc) to clock enable (key) hold time 0.0 0.0 ns t kco-ro register output, key clock to output data valid 7.5 9.5 ns t kpzh-it t kpzl-it input enable (key) to data valid 11.0 13.5 ns 23 t kpzh-ot t kpzl-ot output enable (key) to data valid 9.0 11.0 ns 24 t kphz-ot t kplz-ot output enable (key) to output at high z (1) 9.0 11.0 ns t kw-li latch input, minimum pulse width of key as latch enable, low or high 6.0 7.0 ns t ks-li latch input, data setup time to latch enable (key) trailing edge 3.0 3.5 ns t kh-li latch input, data to latch enable (key) trailing edge hold time 2.0 2.0 ns 25 t kco-li latch input, latch enable (key) leading edge to data out 13.0 15.5 ns t kp-lit latch input, transparent mode propagation delay 10.0 12.5 ns t kw-lo latch output, minimum pulse width of key as latch enable, low or high 6.0 7.0 ns t ks-lo latch output, data setup time to latch enable (key) trailing edge 5.0 5.5 ns t kh-lo latch output, data to latch enable (key) trailing edge hold time 0.0 0.0 ns 26 t kco-lo latch output, latch enable (key) leading edge to data out 7.5 9.5 ns t kp-lot latch output, transparent mode propagation delay 10.0 12.5 ns f kcnt key counter, input clock frequency 66 50 mhz t wkcnt key counter clock, pulse width 6.0 7.0 ns t s_kcke key counter, enable setup time to kclk 2.5 3.5 ns t h_kcke key counter, kclk to enable hold time 0.0 0.0 ns t s_krst key counter, reset setup time to kclk 2.5 3.5 ns t h_krst key counter, kclk to reset hold time 0.0 0.0 ns 27 t kclk_oe key counter, clock to output data valid or output high z 9.5 11.5 ns t kclk_ie key counter, clock to input data valid 11.5 14.0 ns t p_kclr key counter, clear to output active / high z delay 11.5 13.5 ns t p_kf1f key counter, force 0x1f to output active / high z delay 10.5 12.5 ns t rc rapidconfigure strobe period 30.0 32.5 ns t w+ -rc , t w- -rc rapidconfigure strobe pulse width 6.0 7.0 ns t s-rc rapidconfigure address and data setup time to strobe 0.0 0.0 ns 28 t h-rc rapidconfigure address and data hold time to strobe 3.0 3.0 ns t p-rc rapidconfigure strobe falling edge to data valid (make connection) 35.0 37.5 ns f jtag jtag clock (tck) frequency 10 10 mhz t w-jtag jtag clock (tck) pulse width 20.0 20.0 ns t s-jtag jtag setup time 4.0 4.0 ns 29 t h-jtag jtag hold time 0.0 0.0 ns t p-jtag jtag clock to output data valid 15.0 15.0 ns speed grade -10 -12 units ref. figure symbol parameter min max min max table 18. ac electrical specifications for iqx320 and iqx240b (continued)
iqx family data sheet february 2001 revision 6.2 33 5.6 ac electrical specifications for iqx160 and iqx128b (t a = 0 c to 70 c, v dd = 5v5%; v dd .pad = 5v5%, or v dd .pad = 3.3v10%. assume two i/o ports connected through the switch matrix with 35 pf external loading.) speed grade -7 -10 units ref. figure symbol parameter min max min max f rio register input/output, clock frequency (1, 2) 133 100 mhz t w-riol register input/output, clock pulse width, low (1, 2) 3.3 4.5 ns t w-rioh register input/output, clock pulse width, high (1, 2) 3.3 1000 4.5 1000 ns t s-rio register input/output, data setup time to clk 2.0 3.0 ns 13 t h-rio register input/output, clk to data hold time 0.0 0.0 ns t co-rio register input/output, clock to output data valid 8.5 10.0 ns f ri register input, clock frequency (1) 100 80 mhz t w-ril register input, clock pulse width, low 3.3 4.5 ns t w-rih register input, clock pulse width, high 3.3 1000 4.5 1000 ns t s-ri register input, data setup time to clk 2.0 3.0 ns 14 t h-ri register input, clk to data hold time 0.0 0.0 ns t co-ri register input, clock to output data valid 12.0 15.0 ns f ro register output, clock pulse frequency (1) 133 100 mhz t w-rol register output, clock width, low 3.3 4.5 ns t w-roh register output, clock width, high 3.3 1000 4.5 1000 ns t s-ro register output, data setup time to clk 3.0 4.0 ns 15 t h-ro register output, clk to data hold time 0.0 0.0 ns t co-ro register output, clock to output data valid 8.5 10.0 ns t phl , t plh one way signal propagation delay 7.5 10.0 ns ? t br additional delay in bus repeater (br) mode (1, 2) 0.0 0.0 ns t sk skew between output ports (1) 1.5 1.5 ns t w+ input flow through positive pulse width (2) 3.5 4.5 ns 16 t w- input flow through negative pulse width (2) 4.5 5.0 ns r data nrz data rate (1, 2) 200 180 mb/s t pzh-it , t pzl-it input enable (gt) to data valid 10.0 12.5 ns 17 t pzh-ot , t pzl-ot output enable (gt) to data valid 9.0 10.0 ns 18 t phz-ot , t plz-ot output enable (gt) to output at high z (1) 7.0 8.5 ns t w-li latch input, latch enable (gc) pulse width, low or high 3.3 4.5 ns t s-li latch input, data setup time to latch enable (gc) trailing edge 2.0 3.0 ns t h-li latch input, data to latch enable (gc) trailing edge hold time 4.0 4.0 ns 19 t co-li latch input, latch enable (gc) leading edge to data out delay 12.0 15.0 ns t p-lit latch input, transparent mode propagation delay 9.0 10.0 ns t w-lo latch output, latch enable (gc) pulse width, low or high 3.3 4.5 ns t s-lo latch output, data setup time to latch enable (gc) trailing edge 4.0 5.0 ns t h-lo latch output, data to latch enable (gc) trailing edge hold time 0.0 0.0 ns 20 t co-lo latch output, latch enable (gc) leading edge to data out delay 35.0 40.0 ns t p-lot latch output, transparent mode propagation delay 8.0 10.0 ns t kw-ri register input, minimum pulse width of key as clock enable, low or high 5.0 6.0 ns t ks-ri register input, clock enable (key) setup time to clk (gc) 2.5 3.0 ns 21 t kh-ri register input, clk (gc) to clock enable (key) hold time 2.0 2.0 ns t kco-ri register input, key clock to output data valid 10.5 13.0 ns table 19. ac electrical specifications for iqx160 and iqx128b
iqx family data sheet 34 revision 6.2 february 2001 notes: (1) these parameters are guaranteed but not tested in production. (2) the timing parameters are specified for a configuration where an input port is driving one output port. for configurations w here an input port is driving two or more output ports, the timing parameters are de-rated as shown in section 5.7 or table 20. these parameters are guaranteed but not tested in production. t kw-ro register output, minimum pulse width of key as clock enable, low or high 5.0 6.0 ns t ks-ro register output, clock enable (key) setup time to clk (gc) 4.5 5.0 ns 22 t kh-ro register output, clk (gc) to clock enable (key) hold time 0.0 0.0 ns t kco-ro register output, key clock to output data valid 6.5 7.5 ns t kpzh-it t kpzl-it input enable (key) to data valid 9.0 11.0 ns 23 t kpzh-ot t kpzl-ot output enable (key) to data valid 7.5 9.0 ns t kphz-ot t kplz-ot output enable (key) to output at high z (1) 7.5 9.0 ns 24 t kw-li latch input, minimum pulse width of key as latch enable, low or high 5.0 6.0 ns t ks-li latch input, data setup time to latch enable (key) trailing edge 2.5 3.0 ns t kh-li latch input, data to latch enable (key) trailing edge hold time 2.0 2.0 ns 25 t kco-li latch input, latch enable (key) leading edge to data out 10.5 13.0 ns t kp-lit latch input, transparent mode propagation delay 7.5 10.0 ns t kw-lo latch output, minimum pulse width of key as latch enable, low or high 5.0 6.0 ns t ks-lo latch output, data setup time to latch enable (key) trailing edge 4.5 5.0 ns t kh-lo latch output, data to latch enable (key) trailing edge hold time 0.0 0.0 ns 26 t kco-lo latch output, latch enable (key) leading edge to data out 6.5 7.5 ns t kp-lot latch output, transparent mode propagation delay 7.5 10.0 ns f kcnt key counter, input clock frequency 80 66 mhz t wkcnt key counter clock, pulse width 5.0 6.0 ns t s_kcke key counter, enable setup time to kclk 2.0 2.5 ns t h_kcke key counter, kclk to enable hold time 0.0 0.0 ns t s_krst key counter, reset setup time to kclk 2.0 2.5 ns t h_krst key counter, kclk to reset hold time 0.0 0.0 ns 27 t kclk_oe key counter, clock to output data valid or output high z 8.0 9.5 ns t kclk_ie key counter, clock to input data valid 9.5 11.5 ns t p_kclr key counter, clear to output active / high z delay 9.5 11.5 ns t p_kf1f key counter, force 0x1f to output active / high z delay 8.5 10.5 ns t rc rapidconfigure strobe period 15.0 17.0 ns t w+ -rc , t w- -rc rapidconfigure strobe pulse width 6.0 7.5 ns t s-rc rapidconfigure address and data setup time to strobe 2.0 3.0 ns 28 t h-rc rapidconfigure address and data hold time to strobe 0.0 0.0 ns t p-rc rapidconfigure strobe falling edge to data valid (make connection) 25.0 30.0 ns f jtag jtag clock (tck) frequency 10 10 mhz t w-jtag jtag clock (tck) pulse width 20.0 20.0 ns t s-jtag jtag setup time 4.0 4.0 ns 29 t h-jtag jtag hold time 0.0 0.0 ns t p-jtag jtag clock to output data valid 15.0 15.0 ns speed grade -7 -10 units ref. figure symbol parameter min max min max table 19. ac electrical specifications for iqx160 and iqx128b (continued)
iqx family data sheet february 2001 revision 6.2 35 5.7 parameter de-rating for one-to-many connections symbol parameter iqx320 iqx240b iqx160 iqx128b units min max min max min max min max cn max maximum number of connections per input - 32 - 32 - 32 - 32 ? t pd increase in t pd for every additional output port connected to an input port - 0.35 - 0.35 - 0.25 - 0.25 ns ? t w increase in tw+ and tw- for every additional output port connected to an input port - 200 - 200 - 160 - 160 ps ? f decrease in maximum operating frequency every additional output port connected to an input port -1-1-0.75-0.75mhz table 20. parameter de-rating for one-to-many connections
iqx family data sheet 36 revision 6.2 february 2001 5.8 test circuit and timing diagrams figure 12. test circuit and waveform definition figure 13. registered input and registered output mode timing (iclk, oclk synchronized) figure 14. registered input mode timing 50 ? v dd .pad 500 ? 35pf* pulse generator d.u.t. vin vout 500 ? 7.0v * load capacitance includes jig and probe capacitance. t plz /t pzl closed all others open parameter tested switch position 3.0v 1.5v 0v t r t f t r t f t w 90% 10% negative pulse 3.0v 1.5v 0v 90% 10% positive pulse t f = 3 ns (max) t r = 3 ns (max) d n d n+1 t co-rio d n-2 d n d n-1 outport t w-rioh t w-riol t s-rio t h-rio gc (clk) inport d ce q out port d ce q clk inport switch matrix ri ro t co-ri outport t w-rih t w-ril t s-ri t h-ri gc (clk) inport d n-1 d n d n+1 d n d n+1 ri op inport outport switch matrix d ce q clk
iqx family data sheet february 2001 revision 6.2 37 figure 15. registered output mode timing figure 16. i/o port timing (flow?through mode) figure 17. input enable timing (flow?through mode) t co-ro d n-1 d n d n+1 d n d n+1 outport t w-roh t w-rol t s-ro t h-ro gc (clk) inport inport out port ro in switch matrix d ce q clk 1.5v inport 1 inport 2 outport 1 outport 2 t sk t sk t plh t w+ t phl inport 1 in op outport 1 switch matrix inport 2 outport 2 gt (ie) outport t pzh-it t pzl-it inport ie in op outport inport switch matrix
iqx family data sheet 38 revision 6.2 february 2001 figure 18. output enable timing (flow ? through mode) figure 19. latched input mode timing figure 20. latched output mode timing gt (oe) outport t pzh-ot t pzl-ot t plz-ot t phz-ot v ol + 0.3v v oh - 0.3v v ol v oh inport oe in op outport inport switch matrix switch matrix op inport outport t co-li t p-lit t s-li t h-li t w-li gc (clk) inport outport li d le q clk switch matrix lo inport outport in t co-lo t p-lot t s-lo t h-lo t w-lo gc (clk) inport outport d le q clk
iqx family data sheet february 2001 revision 6.2 39 figure 21. key timing for register input, clock enable (cke) figure 22. key timing for register output, clock enable (cke) figure 23. key timing for input enable inport outport ri op switch matrix t ks-ri t kh-ri gc (clk) key (cke ) inport outport valid t kw-ri t kco-ri d ce q clk cke inport outport ro in switch matrix t ks-ro t kh-ro gc (clk) key (cke) inport outport valid t kw-ro t kco-ro d ce q clk cke key (ie) valid valid outport t kpzh-it t kpzl-it inport ie in op outport inport switch matrix
iqx family data sheet 40 revision 6.2 february 2001 figure 24. key timing for output enable figure 25. key timing for latch input, enable (cke) figure 26. key timing for latch output, enable (cke) key (oe) outport t kpzh-ot t kpzl-ot t kplz-ot t kphz-ot v ol + 0.3v v oh - 0.3v v ol v oh inport oe in op outport inport valid valid switch matrix inport outport li op switch matrix t kco-li t ks-li t kh-li gc (clk) key (cke) inport outport valid t kp-lit d le q clk cke t kco-lo t ks-lo t kh-lo gc (clk) key (cke) inport outport valid t kp-lot switch matrix in lo inport d le q clk cke outport
iqx family data sheet february 2001 revision 6.2 41 figure 27. key counter timing figure 28. rapidconfigure timing k0/kclk k1/kcke k2/krst k3/kclr k4/k1f key bus (internal) tg1* tg2* tg1* 0 1 0 1 2 1f 0 abcdefghjmnprt * tg1 and tg2 are the 5-bit tag values programmed in the i/o ports outport1 and inport2 respectively. t h_kcke t s_krst t h_krst outport2 t kclk_ie inport2 t kclk_ie v ol outport1 t kclk_oe t kclk_oe v ol + 0.3v t s_kcke inport1 oe in op outport1 switch matrix inport2 in op outport2 switch matrix ie t kclk_oe v oh - 0.3v v oh t kclk_oe t rc t s-rc t p-rc t h-rc t s-rc t s-rc t h-rc t h-rc t s-rc t s-rc t w+rc t w-rc strobe output port we make connection break connection ra[7:0] ca[3:0] p/s, c1, c0
iqx family data sheet 42 revision 6.2 february 2001 figure 29. jtag timing t p-jtag t s-jtag t h-jtag t w-jtag t w-jtag tck tdi, tms tdo
iqx family data sheet february 2001 revision 6.2 43 6.0 p inout 6.1 iqx320 [pbga/416l] package pinout by name name pin# name pin# name pin# name pin# name pin# name pin# name pin# name pin# gc0 e2 p043 a18 p095 g26 p147 aa26 p199 af15 p251 ab3 p303/ca7 h3 v dd .pad3 af23 gc1 d1 p044 e15 p096 k24 p148 w23 p200 ad14 p252 x5 p304/ca8 l5 v dd .pad4 e1 gc2 e3 p045 b18 p097 g27 p149 aa25 p201 ae15 p253 ac1 p305 g1 v dd .pad4 h4 gc3 c3 p046 c16 p098 k25 p150 y23 p202 ab14 p254 x4 p306/ra0 k4 v dd .pad4 j1 gt0 d22 p047 c18 p099 h25 p151 ac27 p203 ae14 p255 ab2 p307/ra1 g2 v dd .pad4 n2 gt1 e24 p048 d16 p100 l23 p152 u23 p204 ac14 p256 w5 p308/ra2 k5 v dd .pad4 p1 gt2 ab5 p049 b19 p101 h26 p153 ab25 p205 ae13 p257 aa3 p309/ra3 g3 v dd .pad4 r2 gt3 aa5 p050 e16 p102 l24 p154 aa24 p206 ad13 p258 w4 p310/ra4 j4 v dd .pad4 r3 gt4 d2 p051 c19 p103 j25 p155 ac26 p207 ae12 p259 aa2 p311/ra5 f2 v dd .pad4 v1 p000 d5 p052 c17 p104 l25 p156 aa23 p208 ac13 p260/gt12 v5 p312/ra6 j5 v dd .pad4 x1 p001 e14 p053 b20 p105 j26 p157 ad25 p209 ae11 p261/gt11 y3 p313/ra7 h5 v dd .pad4 ab1 p002 e6 p054 d17 p106 m25 p158 ab23 p210 ab13 p262 v4 p314/ra8 g4 v dd .x f3 p003 e11 p055 c20 p107 j27 p159 ac25 p211 af10 p263/gt10 y2 p315/p/ s g5 v ss a6 p004 d6 p056 e17 p108 m23 p160 ab22 p212 ac12 p264 v3 p316/c0 f4 v ss a11 p005 e9 p057 a21 p109 k26 p161 ad24 p213 ae10 p265/gt9 y1 p317/c1 f5 v ss a12 p006 e8 p058 d18 p110 m24 p162 ac23 p214 ab12 p266 u5 p318/we e5 v ss a16 p007 c6 p059 b21 p111 l26 p163 ae25 p215 ad10 p267/gt8 x3 p319/strobe d3 v ss a17 p008 e7 p060 d19 p112 n23 p164 ab21 p216 ac11 p268/gc12 u4 rce c4 v ss a20 p009 b6 p061 c21 p113 m26 p165 ae24 p217 ae9 p269/gc11 x2 tck a4 v ss a22 p010 d7 p062 e18 p114 n24 p166 ac22 p218 ac10 p270/gc10 u3 tdi b3 v ss aa1 p011 c7 p063 b22 p115 n27 p167 ad23 p219 ad9 p271/gc9 w3 tdo c5 v ss aa27 p012 e10 p064 e19 p116 p25 p168 ac21 p220 ac9 p272/gc8 t5 tms b4 v ss ab24 p013 b7 p065 c22 p117 n26 p169 af24 p221 ae8 p273/k4 w1 trst* b5 v ss ab26 p014 d9 p066 d20 p118 p23 p170 ab20 p222 ab11 p274 t4 v dd a19 v ss ac4 p015 a7 p067 b23 p119 r26 p171 ae23 p223 ad8 p275/k3 v2 v dd h27 v ss ac24 p016 d8 p068 e20 p120 p24 p172 ac20 p224 ac8 p276 t3 v dd w2 v ss ad26 p017 c8 p069 a24 p121 r27 p173 ad22 p225 af7 p277/k2 u2 v dd ad12 v ss ae3 p018 d10 p070 d21 p122 r25 p174 ab19 p226 ab10 p278 r4 v dd .pad1 a5 v ss af6 p019 b8 p071 c23 p123 t26 p175 ae22 p227 ae7 p279/k1 t2 v dd .pad1 a8 v ss af8 p020 c10 p072 e21 p124 r24 p176 ac19 p228 ab8 p280 r5 v dd .pad1 a10 v ss af11 p021 c9 p073 b24 p125 u26 p177 ad21 p229 ad7 p281/k0 r1 v dd .pad1 a14 v ss af12 p022 d11 p074 e22 p126 r23 p178 ab18 p230 ab9 p282 p3 v dd .pad1 a23 v ss af16 p023 b9 p075 c25 p127 v27 p179 ae21 p231 ae6 p283/gc7 p2 v dd .pad1 b13 v ss af17 p024 c11 p076 c24 p128 t25 p180 ac18 p232 ab7 p284 p4 v dd .pad1 b15 v ss af22 p025 a9 p077 d25 p129 v26 p181 af21 p233 ad6 p285/gc6 n1 v dd .pad1 c13 v ss b25 p026 e12 p078 e23 p130 t24 p182 ad18 p234 ac7 p286 n3 v dd .pad2 e27 v ss c2 p027 b10 p079 c26 p131 v25 p183 ad20 p235 ae5 p287/gc5 m2 v dd .pad2 f23 v ss d4 p028 d12 p080 f24 p132 t23 p184 ab17 p236 ac6 p288 p5 v dd .pad2 k27 v ss d23 p029 b11 p081 d26 p133 w26 p185 ae20 p237 af4 p289/gc4 l2 v dd .pad2 n25 v ss d24 p030 c12 p082 g23 p134 u25 p186 ac17 p238 ab6 p290 n4 v dd .pad2 p26 v ss e4 p031 b12 p083 e25 p135 w25 p187 ad19 p239 ad5 p291gt7 k1 v dd .pad2 p27 v ss f1 p032 e13 p084 g24 p136 u24 p188 ad17 p240 ac5 p292 m3 v dd .pad2 w27 v ss f27 p033 a13 p085 d27 p137 x26 p189 ae19 p241 ae4 p293/gt6 k2 v dd .pad2 x24 v ss h1 p034 d13 p086 h23 p138 v24 p190 ab16 p242 ad3 p294 l3 v dd .pad2 ab27 v ss l1 p035 b14 p087 e26 p139 x25 p191 af19 p243 ad4 p295/gt5 k3 v dd .pad3 ad11 v ss l27 p036 c14 p088 h24 p140 w24 p192 ac16 p244 ab4 p296/ca0 n5 v dd .pad3 ad15 v ss m1 p037 a15 p089 f25 p141 y27 p193 ae18 p245 ac3 p297/ca1 j2 v dd .pad3 af5 v ss m27 p038 d14 p090 j23 p142 v23 p194 ad16 p246 aa4 p298/ca2 m5 v dd .pad3 af9 v ss t1 p039 b16 p091 f26 p143 y26 p195 ae17 p247 ad2 p299/ca3 j3 v dd .pad3 af13 v ss t27 p040 c15 p092 j24 p144 y24 p196 ac15 p248 y5 p300/ca4 m4 v dd .pad3 af14 v ss u1 p041 b17 p093 g25 p145 y25 p197 ae16 p249 ac2 p301/ca5 h2 v dd .pad3 af18 v ss u27 p042 d15 p094 k23 p146 x23 p198 ab15 p250 y4 p302/ca6 l4 v dd .pad3 af20 v ss x27 table 21. iqx320 [pbga/416l] package pinout by name
iqx family data sheet 44 revision 6.2 february 2001 6.2 iqx320 [pbga/416l] package pinout by location pin# name pin# name pin# name pin# name pin# name pin# name pin# name pin# name a4 tck c11 p024 e11 p003 j24 p092 p27 v dd .pad2 x3 p267/gt8 ab26 v ss ad26 v ss a5 v dd .pad1 c12 p030 e12 p026 j25 p103 r1 p281/k0 x4 p254 ab27 v dd .pad2 ae3 v ss a6 v ss c13 v dd .pad1 e13 p032 j26 p105 r2 v dd .pad4 x5 p252 ac1 p253 ae4 p241 a7 p015 c14 p036 e14 p001 j27 p107 r3 v dd .pad4 x23 p146 ac2 p249 ae5 p235 a8 v dd .pad1 c15 p040 e15 p044 k1 p291/gt7 r4 p278 x24 v dd .pad2 ac3 p245 ae6 p231 a9 p025 c16 p046 e16 p050 k2 p293/gt6 r5 p280 x25 p139 ac4 v ss ae7 p227 a10 v dd .pad1 c17 p052 e17 p056 k3 p295/gt5 r23 p126 x26 p137 ac5 p240 ae8 p221 a11 v ss c18 p047 e18 p062 k4 p306/ra0 r24 p124 x27 v ss ac6 p236 ae9 p217 a12 v ss c19 p051 e19 p064 k5 p308/ra2 r25 p122 y1 p265/gt9 ac7 p234 ae10 p213 a13 p033 c20 p055 e20 p068 k23 p094 r26 p119 y2 p263/gt10 ac8 p224 ae11 p209 a14 v dd .pad1 c21 p061 e21 p072 k24 p096 r27 p121 y3 p261/gt11 ac9 p220 ae12 p207 a15 p037 c22 p065 e22 p074 k25 p098 t1 v ss y4 p250 ac10 p218 ae13 p205 a16 v ss c23 p071 e23 p078 k26 p109 t2 p279/k1 y5 p248 ac11 p216 ae14 p203 a17 v ss c24 p076 e24 gt1 k27 v dd .pad2 t3 p276 y23 p150 ac12 p212 ae15 p201 a18 p043 c25 p075 e25 p083 l1 v ss t4 p274 y24 p144 ac13 p208 ae16 p197 a19 v dd c26 p079 e26 p087 l2 p289/gc4 t5 p272/gc8 y25 p145 ac14 p204 ae17 p195 a20 v ss d1 gc1 e27 v dd .pad2 l3 p294 t23 p132 y26 p143 ac15 p196 ae18 p193 a21 p057 d2 gt4 f1 v ss l4 p302/ca6 t24 p130 y27 p141 ac16 p192 ae19 p189 a22 v ss d3 p319/strobe f2 p311/ra5 l5 p304/ca8 t25 p128 aa1 v ss ac17 p186 ae20 p185 a23 v dd .pad1 d4 v ss f3 v dd .x l23 p100 t26 p123 aa2 p259 ac18 p180 ae21 p179 a24 p069 d5 p000 f4 p316/c0 l24 p102 t27 v ss aa3 p257 ac19 p176 ae22 p175 b3 tdi d6 p004 f5 p317/c1 l25 p104 u1 v ss aa4 p246 ac20 p172 ae23 p171 b4 tms d7 p010 f23 v dd .pad2 l26 p111 u2 p277/k2 aa5 gt3 ac21 p168 ae24 p165 b5 trst* d8 p016 f24 p080 l27 v ss u3 p270/gc10 aa23 p156 ac22 p166 ae25 p163 b6 p009 d9 p014 f25 p089 m1 v ss u4 p268/gc12 aa24 p154 ac23 p162 af4 p237 b7 p013 d10 p018 f26 p091 m2 p287/gc5 u5 p266 aa25 p149 ac24 v ss af5 v dd .pad3 b8 p019 d11 p022 f27 v ss m3 p292 u23 p152 aa26 p147 ac25 p159 af6 v ss b9 p023 d12 p028 g1 p305 m4 p300/ca4 u24 p136 aa27 v ss ac26 p155 af7 p225 b10 p027 d13 p034 g2 p307/ra1 m5 p298/ca2 u25 p134 ab1 v dd .pad4 ac27 p151 af8 v ss b11 p029 d14 p038 g3 p309/ra3 m23 p108 u26 p125 ab2 p255 ad2 p247 af9 v dd .pad3 b12 p031 d15 p042 g4 p314/ra8 m24 p110 u27 v ss ab3 p251 ad3 p242 af10 p211 b13 v dd .pad1 d16 p048 g5 p315/p/s m25 p106 v1 v dd .pad4 ab4 p244 ad4 p243 af11 v ss b14 p035 d17 p054 g23 p082 m26 p113 v2 p275/k3 ab5 gt2 ad5 p239 af12 v ss b15 v dd .pad1 d18 p058 g24 p084 m27 v ss v3 p264 ab6 p238 ad6 p233 af13 v dd .pad3 b16 p039 d19 p060 g25 p093 n1 p285/gc6 v4 p262 ab7 p232 ad7 p229 af14 v dd .pad3 b17 p041 d20 p066 g26 p095 n2 v dd .pad4 v5 p260/gt12 ab8 p228 ad8 p223 af15 p199 b18 p045 d21 p070 g27 p097 n3 p286 v23 p142 ab9 p230 ad9 p219 af16 v ss b19 p049 d22 gt0 h1 v ss n4 p290 v24 p138 ab10 p226 ad10 p215 af17 v ss b20 p053 d23 v ss h2 p301/ca5 n5 p296/ca0 v25 p131 ab11 p222 ad11 v dd .pad3 af18 v dd .pad3 b21 p059 d24 v ss h3 p303/ca7 n23 p112 v26 p129 ab12 p214 ad12 v dd af19 p191 b22 p063 d25 p077 h4 v dd .pad4 n24 p114 v27 p127 ab13 p210 ad13 p206 af20 v dd .pad3 b23 p067 d26 p081 h5 p313/ra7 n25 v dd .pad2 w1 p273/k4 ab14 p202 ad14 p200 af21 p181 b24 p073 d27 p085 h23 p086 n26 p117 w2 v dd ab15 p198 ad15 v dd .pad3 af22 v ss b25 v ss e1 v dd .pad4 h24 p088 n27 p115 w3 p271/gc9 ab16 p190 ad16 p194 af23 v dd .pad3 c2 v ss e2 gc0 h25 p099 p1 v dd .pad4 w4 p258 ab17 p184 ad17 p188 af24 p169 c3 gc3 e3 gc2 h26 p101 p2 p283/gc7 w5 p256 ab18 p178 ad18 p182 c4 rce e4 v ss h27 v dd p3 p282 w23 p148 ab19 p174 ad19 p187 c5 tdo e5 p318/we j1 v dd .pad4 p4 p284 w24 p140 ab20 p170 ad20 p183 c6 p007 e6 p002 j2 p297/ca1 p5 p288 w25 p135 ab21 p164 ad21 p177 c7 p011 e7 p008 j3 p299/ca3 p23 p118 w26 p133 ab22 p160 ad22 p173 c8 p017 e8 p006 j4 p310/ra4 p24 p120 w27 v dd .pad2 ab23 p158 ad23 p167 c9 p021 e9 p005 j5 p312/ra6 p25 p116 x1 v dd .pad4 ab24 v ss ad24 p161 c10 p020 e10 p012 j23 p090 p26 v dd .pad2 x2 p269/gc11 ab25 p153 ad25 p157 table 22. iqx320 [pbga/416l] package pinout by location
iqx family data sheet february 2001 revision 6.2 45 6.3 iqx320 [pbga/416l] package footprint notes: (1) v dd 1 - v dd .pad1 (2) v dd 2 - v dd .pad2 (3) v dd 3 - v dd .pad3 (4) v dd 4 - v dd .pad4 (5) pxxx/ - port is dual function af ae ad ac ab aa y x w v u t r p n m l k j h g f e d c b a 1 p253 v dd 4 v ss p265 / v dd 4 p273/ v dd 4 v ss v ss p281/ v dd 4 p285/ v ss v ss p291/ v dd 4 v ss p305 v ss v dd 4gc1 1 2 p247 p249 p255 p259 p263 / p269/ v dd p275/ p277 / p279 / v dd 4 p283/ v dd 4 p287 / p289 / p293/ p297/ p301/ p307 / p311/ gc0 gt4 v ss 2 3 v ss p242 p245 p251 p257 p261 / p267/ p271/ p264 p270 / p276 v dd 4 p282 p286 p292 p294 p295/ p299/ p303/ p309 / v dd .x gc2 p319 / gc3 tdi 3 4 p237 p241 p243 v ss p244 p246 p250 p254 p258 p262 p268 / p274 p278 p284 p290 p300 / p302 / p306/ p310/ v dd 4p314 / p316/ v ss v ss rce tms tck 4 5 v dd 3 p235 p239 p240 gt2 gt3 p248 p252 p256 p260/ p266 p272 / p280 p288 p296/ p298 / p304 / p308/ p312/ p313/ p315 / p317/ p318/ p000 tdo trst * v dd 1 5 6 v ss p231 p233 p236 p238 p002 p004 p007 p009 v ss 6 7 p225 p227 p229 p234 p232 p008 p010 p011 p013 p015 7 8 v ss p221 p223 p224 p228 p006 p016 p017 p019 v dd 1 8 9 v dd 3 p217 p219 p220 p230 p005 p014 p021 p023 p025 9 10 p211 p213 p215 p218 p226 p012 p018 p020 p027 v dd 1 10 11 v ss p209 v dd 3 p216 p222 p003 p022 p024 p029 v ss 11 12 v ss p207 v dd p212 p214 p026 p028 p030 p031 v ss 12 13 v dd 3 p205 p206 p208 p210 p032 p034 v dd 1 v dd 1p033 13 14 v dd 3 p203 p200 p204 p202 p001 p038 p036 p035 v dd 1 14 15 p199 p201 v dd 3 p196 p198 p044 p042 p040 v dd 1p037 15 16 v ss p197 p194 p192 p190 p050 p048 p046 p039 v ss 16 17 v ss p195 p188 p186 p184 p056 p054 p052 p041 v ss 17 18 v dd 3 p193 p182 p180 p178 p062 p058 p047 p045 p043 18 19 p191 p189 p187 p176 p174 p064 p060 p051 p049 v dd 19 20 v dd 3 p185 p183 p172 p170 p068 p066 p055 p053 v ss 20 21 p181 p179 p177 p168 p164 p072 p070 p061 p059 p057 21 22 v ss p175 p173 p166 p160 p074 gt0 p065 p063 v ss 22 23 v dd 3 p171 p167 p162 p158 p156 p150 p146 p148 p142 p152 p132 p126 p118 p112 p108 p100 p094 p090 p086 p082 v dd 2p078 v ss p071 p067 v dd 1 23 24 p169 p165 p161 v ss v ss p154 p144 v dd 2 p140 p138 p136 p130 p124 p120 p114 p110 p102 p096 p092 p088 p084 p080 gt1 v ss p076 p073 p069 24 25 p163 p157 p159 p153 p149 p145 p139 p135 p131 p134 p128 p122 p116 v dd 2 p106 p104 p098 p103 p099 p093 p089 p083 p077 p075 v ss 25 26 v ss p155 v ss p147 p143 p137 p133 p129 p125 p123 p119 v dd 2 p117 p113 p111 p109 p105 p101 p095 p091 p087 p081 p079 26 27 p151 v dd 2 v ss p141 v ss v dd 2 p127 v ss v ss p121 v dd 2p115 v ss v ss v dd 2p107 v dd p097 v ss v dd 2p085 27 af ae ad ac ab aa y x w v u t r p n m l k j h g f e d c b a figure 30. iqx320 [pbga/416l] package footprint
iqx family data sheet 46 revision 6.2 february 2001 6.4 iqx240b [pqfp/304l] package pinout by name name pin# name pin# name pin# name pin# name pin# name pin# name pin# name pin# gc0 12 p029 262 p067 215 p105 171 p143 125 p181 78 p219/ca3 30 v dd. pad2 178 gc1 9 p030 261 p068 214 p106 170 p144 124 p182 75 p220/ca4 29 v dd. pad2 192 gc2 7 p031 260 p069 213 p107 169 p145 123 p183 74 p221/ca5 27 v dd. pad2 221 gc3 3 p032 259 p070 212 p108 168 p146 122 p184 73 p222/ca6 26 v dd. pad3 84 gt0 229 p033 258 p071 209 p109 167 p147 121 p185 72 p223/ca7 25 v dd. pad3 147 gt1 228 p034 257 p072 208 p110 164 p148 120 p186 70 p224/ca8 24 v dd. pad3 101 gt2 77 p035 256 p073 207 p111 163 p149 117 p187 69 p225 23 v dd. pad3 119 gt3 76 p036 255 p074 206 p112 162 p150 116 p188 68 p226/ra0 22 v dd. pad3 131 gt4 5 p037 254 p075 205 p113 161 p151 115 p189 67 p227/ra1 19 v dd. pad4 20 p000 303 p038 251 p076 204 p114 160 p152 114 p190 66 p228/ra2 18 v dd. pad4 35 p001 300 p039 250 p077 203 p115 157 p153 111 p191 65 p229/ra3 17 v dd. pad4 48 p002 295 p040 249 p078 202 p116 156 p154 110 p192 64 p230/ra4 16 v dd. pad4 60 p003 293 p041 248 p079 201 p117 155 p155 109 p193 63 p231/ra5 15 v dd. x28 p004 292 p042 247 p080 200 p118 154 p156 108 p194/gt12 62 p232/ra6 14 v ss 10 p005 291 p043 246 p081 199 p119 153 p157 107 p195/gt11 59 p233/ra7 13 v ss 21 p006 290 p044 245 p082 198 p120 152 p158 106 p196/gt10 58 p234/ra8 11 v ss 36 p007 288 p045 244 p083 197 p121 151 p159 105 p197/gt9 57 p235/p/ s 8v ss 49 p008 287 p046 243 p084 196 p122 150 p160 104 p198/gt8 55 p236/c0 6 v ss 61 p009 286 p047 240 p085 195 p123 149 p161 103 p199/gc12 54 p237/c1 4 v ss 71 p010 285 p048 239 p086 194 p124 148 p162 102 p200/gc11 53 p238/we 2 v ss 83 p011 284 p049 238 p087 191 p125 145 p163 99 p201/gc10 52 p239/strobe 1 v ss 90 p012 283 p050 237 p088 190 p126 144 p164 98 p202/gc9 51 rce 304 v ss 100 p013 282 p051 236 p089 189 p127 143 p165 97 p203/gc8 50 tck 298 v ss 112 p014 281 p052 234 p090 188 p128 142 p166 96 p204/k4 47 tdi 302 v ss 118 p015 280 p053 233 p091 187 p129 141 p167 95 p205/k3 46 tdo 299 v ss 130 p016 277 p054 232 p092 186 p130 140 p168 94 p206/k2 45 tms 301 v ss 146 p017 276 p055 231 p093 185 p131 139 p169 93 p207/k1 44 trst* 294 v ss 159 p018 275 p056 230 p094 184 p132 138 p170 92 p208/k0 43 v dd 56 v ss 166 p019 274 p057 227 p095 183 p133 137 p171 91 p209/gc7 42 v dd 113 v ss 179 p020 273 p058 226 p096 182 p134 136 p172 89 p210/gc6 41 v dd 210 v ss 193 p021 272 p059 225 p097 181 p135 135 p173 88 p211/gc5 40 v dd 242 v ss 211 p022 271 p060 224 p098 180 p136 134 p174 87 p212/gc4 39 v dd. pad1 235 v ss 222 p023 270 p061 223 p099 177 p137 133 p175 86 p213/gt7 38 v dd. pad1 253 v ss 241 p024 269 p062 220 p100 176 p138 132 p176 85 p214/gt6 37 v dd. pad1 267 v ss 252 p025 268 p063 219 p101 175 p139 129 p177 82 p215/gt5 34 v dd. pad1 279 v ss 266 p026 265 p064 218 p102 174 p140 128 p178 81 p216/ca0 33 v dd. pad1 297 v ss 278 p027 264 p065 217 p103 173 p141 127 p179 80 p217/ca1 32 v dd. pad2 158 v ss 289 p028 263 p066 216 p104 172 p142 126 p180 79 p218/ca2 31 v dd. pad2 165 v ss 296 table 23. iqx240b [pqfp/304l] package pinout by name
iqx family data sheet february 2001 revision 6.2 47 6.5 iqx240b [pqfp/304l] package pinout by location pin# name pin# name pin# name pin# name pin# name pin# name pin# name pin# name 1 p239/strobe 39 p212/gc4 77 gt2 115 p151 153 p119 191 p087 229 gt0 267 v dd. pad1 2 p238/we 40 p211/gc5 78 p181 116 p150 154 p118 192 v dd. pad2 230 p056 268 p025 3 gc3 41 p210/gc6 79 p180 117 p149 155 p117 193 v ss 231 p055 269 p024 4 p237/c1 42 p209/gc7 80 p179 118 v ss 156 p116 194 p086 232 p054 270 p023 5 gt4 43 p208/k0 81 p178 119 v dd. pad3 157 p115 195 p085 233 p053 271 p022 6 p236/c0 44 p207/k1 82 p177 120 p148 158 v dd. pad2 196 p084 234 p052 272 p021 7 gc2 45 p206/k2 83 v ss 121 p147 159 v ss 197 p083 235 v dd. pad1 273 p020 8 p235/p/ s 46 p205/k3 84 v dd. pad3 122 p146 160 p114 198 p082 236 p051 274 p019 9 gc1 47 p204/k4 85 p176 123 p145 161 p113 199 p081 237 p050 275 p018 10 v ss 48 v dd. pad4 86 p175 124 p144 162 p112 200 p080 238 p049 276 p017 11 p234/ra8 49 v ss 87 p174 125 p143 163 p111 201 p079 239 p048 277 p016 12 gc0 50 p203/gc8 88 p173 126 p142 164 p110 202 p078 240 p047 278 v ss 13 p233/ra7 51 p202/gc9 89 p172 127 p141 165 v dd. pad2 203 p077 241 v ss 279 v dd. pad1 14 p232/ra6 52 p201/gc10 90 v ss 128 p140 166 v ss 204 p076 242 v dd 280 p015 15 p231/ra5 53 p200/gc11 91 p171 129 p139 167 p109 205 p075 243 p046 281 p014 16 p230/ra4 54 p199/gc12 92 p170 130 v ss 168 p108 206 p074 244 p045 282 p013 17 p229/ra3 55 p198/gt8 93 p169 131 v dd. pad3 169 p107 207 p073 245 p044 283 p012 18 p228/ra2 56 v dd 94 p168 132 p138 170 p106 208 p072 246 p043 284 p011 19 p227/ra1 57 p197/gt9 95 p167 133 p137 171 p105 209 p071 247 p042 285 p010 20 v dd. pad4 58 p196/gt10 96 p166 134 p136 172 p104 210 v dd 248 p041 286 p009 21 v ss 59 p195/gt11 97 p165 135 p135 173 p103 211 v ss 249 p040 287 p008 22 p226/ra0 60 v dd. pad4 98 p164 136 p134 174 p102 212 p070 250 p039 288 p007 23 p225 61 v ss 99 p163 137 p133 175 p101 213 p069 251 p038 289 v ss 24 p224/ca8 62 p194/gt12 100 v ss 138 p132 176 p100 214 p068 252 v ss 290 p006 25 p223/ca7 63 p193 101 v dd. pad3 139 p131 177 p099 215 p067 253 v dd. pad1 291 p005 26 p222/ca6 64 p192 102 p162 140 p130 178 v dd. pad2 216 p066 254 p037 292 p004 27 p221/ca5 65 p191 103 p161 141 p129 179 v ss 217 p065 255 p036 293 p003 28 v dd. x 66 p190 104 p160 142 p128 180 p098 218 p064 256 p035 294 trst* 29 p220/ca4 67 p189 105 p159 143 p127 181 p097 219 p063 257 p034 295 p002 30 p219/ca3 68 p188 106 p158 144 p126 182 p096 220 p062 258 p033 296 v ss 31 p218/ca2 69 p187 107 p157 145 p125 183 p095 221 v dd. pad2 259 p032 297 v dd. pad1 32 p217/ca1 70 p186 108 p156 146 v ss 184 p094 222 v ss 260 p031 298 tck 33 p216/ca0 71 v ss 109 p155 147 v dd. pad3 185 p093 223 p061 261 p030 299 tdo 34 p215/gt5 72 p185 110 p154 148 p124 186 p092 224 p060 262 p029 300 p001 35 v dd. pad4 73 p184 111 p153 149 p123 187 p091 225 p059 263 p028 301 tms 36 v ss 74 p183 112 v ss 150 p122 188 p090 226 p058 264 p027 302 tdi 37 p214/gt6 75 p182 113 v dd 151 p121 189 p089 227 p057 265 p026 303 p000 38 p213/gt7 76 gt3 114 p152 152 p120 190 p088 228 gt1 266 v ss 304 rce table 24. iqx240b [pqfp/304l] package pinout by location
iqx family data sheet 48 revision 6.2 february 2001 6.6 iqx240b [pqfp/304l] package pinout figure 31. iqx240b [ pqfp/ 304l] package pinout 39/strobe p238/we gc3 p237/c1 gt4 p236/c0 gc2 p235/ p/s gc1 v ss p234/ra8 gc0 p233/ra7 p232/ra6 p231/ra5 p230/ra4 p229/ra3 p228/ra2 p227/ra1 v dd. pad4 v ss p226/ra0 p225 p224/ca8 p223/ca7 p222/ca6 p221/ca5 v dd. x p220/ca4 p219/ca3 p218/ca2 p217/ca1 p216/ca0 p215/gt5 v dd. pad4 v ss p214/gt6 p213/gt7 p212/gc4 p211/gc5 p210/gc6 p209/gc7 p208/k0 p207/k1 p206/k2 p205/k3 p204/k4 v dd. pad4 v ss p203/gc8 p202/gc9 p201/gc10 p200/gc11 p199/gc12 p198/gt8 v dd p197/gt9 p196/gt10 p195/gt11 v dd. pad4 v ss p194/gt12 p193 p192 p191 p190 p189 p188 p187 p186 v ss p185 p184 p183 p182 gt3 rce p000 tdi tms p001 tdo tck v dd. pad1 v ss p002 trst* p003 p004 p005 p006 v ss p007 p008 p009 p010 p011 p012 p013 p014 p015 v dd. pad1 v ss p016 p017 p018 p019 p020 p021 p022 p023 p024 p025 v dd. pad1 v ss p026 p027 p028 p029 p030 p031 p032 p033 p034 p035 p036 p037 v dd. pad1 v ss p038 p039 p040 p041 p042 p043 p044 p045 p046 v dd v ss p047 p048 p049 p050 p051 v dd. pad1 p052 p053 p054 p055 p056 gt0 gt2 p181 p180 p179 p178 p177 v ss v dd. pad3 p176 p175 p174 p173 p172 v ss p171 p170 p169 p168 p167 p166 p165 p164 p163 v ss v dd. pad3 p162 p161 p160 p159 p158 p157 p156 p155 p154 p153 v ss v dd p152 p151 p150 p149 v ss v dd. pad3 p148 p147 p146 p145 p144 p143 p142 p141 p140 p139 v ss v dd. pad3 p138 p137 p136 p135 p134 p133 p132 p131 p130 p129 p128 p127 p126 p125 v ss v dd. pad3 p124 p123 p122 p121 p120 gt1 p057 p058 p059 p060 p061 v ss v dd. pad2 p062 p063 p064 p065 p066 p067 p068 p069 p070 v ss v dd p071 p072 p073 p074 p075 p076 p077 p078 p079 p080 p081 p082 p083 p084 p085 p086 v ss v dd. pad2 p087 p088 p089 p090 p091 p092 p093 p094 p095 p096 p097 p098 v ss v dd. pad2 p099 p100 p101 p102 p103 p104 p105 p106 p107 p108 p109 v ss v dd. pad2 p110 p111 p112 p113 p114 v ss v dd. pad2 p115 p116 p117 p118 p119 top view i/o ports powered by v dd .pad1 i/o ports powered by v dd .pad3 i/o ports powered by v dd .pad4 i/o ports powered by v dd .pad2 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 304 303 302 301 300 299 298 297 296 295 294 293 292 291 290 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 273 272 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 247 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76
iqx family data sheet february 2001 revision 6.2 49 6.7 iqx160 [pqfp/208l] package pinout by name name pin# name pin# name pin# name pin# gc0 10 p046 145 p098 82 p150/ra2 16 gc1 7 p047 144 p099 81 p151/ra3 15 gt0 157 p048 143 p100 80 p152/ra4 14 gt1 156 p049 142 p101 78 p153/ra5 13 gt2 53 p050 140 p102 77 p154/ra6 12 gt3 52 p051 139 p103 76 p155/ra7 11 p000 203 p052 138 p104/gt12 74 p156/c0 5 p001 202 p053 137 p105/gt11 73 p157/c1 4 p002 201 p054 136 p106/gt10 72 p158/we 3 p003 200 p055 135 p107 71 p159/strobe 2 p004 198 p056 132 p108/gt9 70 rce 6 p005 197 p057 131 p109/gt8 69 tck 206 p006 196 p058 130 p110/gc12 67 tdi 1 p007 195 p059 129 p111/gc11 66 tdo 207 p008 194 p060 128 p112/gc10 65 tms 208 p009 192 p061 127 p113 64 trst* 204 p010 191 p062 125 p114/gc9 63 v dd 29 p011 190 p063 124 p115/gc8 62 v dd 133 p012 189 p064 123 p116/k4 59 v dd. pad1 119 p013 188 p065 122 p117/k3 58 v dd. pad1 164 p014 187 p066 121 p118 57 v dd. pad1 186 p015 184 p067 120 p119 56 v dd. pad1 205 p016 183 p068 117 p120/k2 55 v dd. pad2 8 p017 182 p069 116 p121/k1 54 v dd. pad2 45 p018 181 p070 115 p122/k0 51 v dd. pad2 61 p019 180 p071 114 p123 50 v dd. pad2 79 p020 179 p072 113 p124 49 v dd. pad2 98 p021 177 p073 112 p125/gc7 48 v dd. x 148 p022 176 p074 110 p126/gc6 47 v ss 9 p023 175 p075 109 p127/gc5 44 v ss 18 p024 174 p076 108 p128/gc4 43 v ss 23 p025 173 p077 107 p129 42 v ss 31 p026 172 p078 106 p130 41 v ss 38 p027 170 p079 105 p131/gt7 40 v ss 46 p028 169 p080 104 p132/gt6 39 v ss 60 p029 168 p081 103 p133/gt5 37 v ss 68 p030 167 p082 102 p134/gt4 36 v ss 75 p031 166 p083 101 p135 35 v ss 83 p032 165 p084 100 p136 34 v ss 90 p033 162 p085 99 p137/gc3 33 v ss 97 p034 161 p086 96 p138/gc2 32 v ss 111 p035 160 p087 95 p139/ p/ s 30 v ss 118 p036 159 p088 94 p140/ca0 28 v ss 126 p037 158 p089 93 p141/ca1 27 v ss 134 p038 155 p090 92 p142/ca2 26 v ss 141 p039 154 p091 91 p143/ca3 25 v ss 149 p040 153 p092 89 p144/ca4 24 v ss 163 p041 152 p093 88 p145/ca5 22 v ss 171 p042 151 p094 87 p146/ca6 21 v ss 178 p043 150 p095 86 p147/ca7 20 v ss 185 p044 147 p096 85 p148/ra0 19 v ss 193 p045 146 p097 84 p149/ra1 17 v ss 199 table 25. iqx160 [pqfp/208l] package pinout by name
iqx family data sheet 50 revision 6.2 february 2001 6.8 iqx160 [pqfp/208l] package pinout by location pin# name pin# name pin# name pin# name 1 tdi 53 gt2 105 p079 157 gt0 2 p159/strobe 54 p121/k1 106 p078 158 p037 3 p158/we 55 p120/k2 107 p077 159 p036 4 p157/c1 56 p119 108 p076 160 p035 5 p156/c0 57 p118 109 p075 161 p034 6 rce 58 p117/k3 110 p074 162 p033 7 gc1 59 p116/k4 111 v ss 163 v ss 8v dd. pad2 60 v ss 112 p073 164 v dd. pad1 9v ss 61 v dd. pad2 113 p072 165 p032 10 gc0 62 p115/gc8 114 p071 166 p031 11 p155/ra7 63 p114/gc9 115 p070 167 p030 12 p154/ra6 64 p113 116 p069 168 p029 13 p153/ra5 65 p112/gc10 117 p068 169 p028 14 p152/ra4 66 p111/gc11 118 v ss 170 p027 15 p151/ra3 67 p110/gc12 119 v dd. pad1 171 v ss 16 p150/ra2 68 v ss 120 p067 172 p026 17 p149/ra1 69 p109/gt8 121 p066 173 p025 18 v ss 70 p108/gt9 122 p065 174 p024 19 p148/ra0 71 p107 123 p064 175 p023 20 p147/ca7 72 p106/gt10 124 p063 176 p022 21 p146/ca6 73 p105/gt11 125 p062 177 p021 22 p145/ca5 74 p104/gt12 126 v ss 178 v ss 23 v ss 75 v ss 127 p061 179 p020 24 p144/ca4 76 p103 128 p060 180 p019 25 p143/ca3 77 p102 129 p059 181 p018 26 p142/ca2 78 p101 130 p058 182 p017 27 p141/ca1 79 v dd. pad2 131 p057 183 p016 28 p140/ca0 80 p100 132 p056 184 p015 29 v dd 81 p099 133 v dd 185 v ss 30 p139/ p/ s 82 p098 134 v ss 186 v dd. pad1 31 v ss 83 v ss 135 p055 187 p014 32 p138/gc2 84 p097 136 p054 188 p013 33 p137/gc3 85 p096 137 p053 189 p012 34 p136 86 p095 138 p052 190 p011 35 p135 87 p094 139 p051 191 p010 36 p134/gt4 88 p093 140 p050 192 p009 37 p133/gt5 89 p092 141 v ss 193 v ss 38 v ss 90 v ss 142 p049 194 p008 39 p132/gt6 91 p091 143 p048 195 p007 40 p131/gt7 92 p090 144 p047 196 p006 41 p130 93 p089 145 p046 197 p005 42 p129 94 p088 146 p045 198 p004 43 p128/gc4 95 p087 147 p044 199 v ss 44 p127/gc5 96 p086 148 v dd. x 200 p003 45 v dd. pad2 97 v ss 149 v ss 201 p002 46 v ss 98 v dd. pad2 150 p043 202 p001 47 p126/gc6 99 p085 151 p042 203 p000 48 p125/gc7 100 p084 152 p041 204 trst* 49 p124 101 p083 153 p040 205 v dd. pad1 50 p123 102 p082 154 p039 206 tck 51 p122/k0 103 p081 155 p038 207 tdo 52 gt3 104 p080 156 gt1 208 tms table 26. iqx160 [pqfp/208l] package pinout by location
iqx family data sheet february 2001 revision 6.2 51 6.9 iqx160 [pqfp/208l] package pinout figure 32. iqx160 [pqfp/208l] package pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 tdi p159/strobe p158/we p157/c1 p156/c0 rce gc1 v dd. pad2 v ss gc0 p155/ra7 p154/ra6 p153/ra5 p152/ra4 p151/ra3 p150/ra2 p149/ra1 v ss p148/ra0 p147/ca7 p146/ca6 p145/ca5 v ss p144/ca4 p143/ca3 p142/ca2 p141/ca1 p140/ca0 v dd p139/ p/s v ss p138/gc2 p137/gc3 p136 p135 p134/gt4 p133/gt5 v ss p132/gt6 p131/gt7 p130 p129 p128/gc4 p127/gc5 v dd. pad2 v ss p126/gc6 p125/gc7 p124 p123 p122/k0 gt3 tms tdo tck v dd. pad1 trst* p000 p001 p002 p003 v ss p004 p005 p006 p007 p008 v ss p009 p010 p011 p012 p013 p014 v dd. pad1 v ss p015 p016 p017 p018 p019 p020 v ss p021 p022 p023 p024 p025 p026 v ss p027 p028 p029 p030 p031 p032 v dd. pad1 v ss p033 p034 p035 p036 p037 gt0 gt2 p121/k1 p120/k2 p119 p118 p117/k3 p116/k4 v ss v dd. pad2 p115/gc8 p114/gc9 p113 p112/gc10 p111/gc11 p110/gc12 v ss p109/gt8 p108/gt9 p107 p106/gt10 p105/gt11 p104/gt12 v ss p103 p102 p101 v dd. pad2 p100 p099 p098 v ss p097 p096 p095 p094 p093 p092 v ss p091 p090 p089 p088 p087 p086 v ss v dd. pad2 p085 p084 p083 p082 p081 p080 gt1 p038 p039 p040 p041 p042 p043 v ss v dd. x p044 p045 p046 p047 p048 p049 v ss p050 p051 p052 p053 p054 p055 v ss v dd p056 p057 p058 p059 p060 p061 v ss p062 p063 p064 p065 p066 p067 v dd. pad1 v ss p068 p069 p070 p071 p072 p073 v ss p074 p075 p076 p077 p078 p079 top view i/o ports powered by v dd .pad2 i/o ports powered by v dd .pad1 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
iqx family data sheet 52 revision 6.2 february 2001 6.10 iqx128b [pqfp/184l] package pinout by name name pin# name pin# name pin# name pin# gc0 10 p040 123 p086/gt10 63 tms 184 gc1 7 p041 122 p087/gt9 62 trst* 179 gt0 139 p042 121 p088/gt8 61 v dd 28 gt1 138 p043 120 p089/gc12 58 v dd 118 gt2 48 p044 117 p090/gc11 57 v dd. pad1 146 gt3 45 p045 116 p091/gc10 56 v dd. pad1 93 p000 178 p046 115 p092/gc9 55 v dd. pad1 106 p001 177 p047 114 p093/gc8 54 v dd. pad1 137 p002 176 p048 113 p094/k4 52 v dd. pad1 157 p003 175 p049 111 p095/k3 51 v dd. pad1 168 p004 173 p050 110 p096/k2 50 v dd. pad1 180 p005 172 p051 109 p097/k1 49 v dd. pad2 47 p006 171 p052 108 p098/k0 44 v dd. pad2 8 p007 170 p053 107 p099/gc7 43 v dd. pad2 18 p008 169 p054 104 p100/gc6 42 v dd. pad2 40 p009 166 p055 103 p101/gc5 39 v dd. pad2 60 p010 165 p056 102 p102 ? /gc4 38 v dd. pad2 73 p011 164 p057 101 p103 ? /gt7 37 v dd. pad2 86 p012 163 p058 100 p104 ? /gt6 36 v dd. x 131 p013 161 p059 98 p105 ? /gt5 34 v ss 41 p014 160 p060 97 p106 ? /gt4 33 v ss 9 p015 159 p061 96 p107 ? /gc3 32 v ss 17 p016 158 p062 95 p108 ? /gc2 31 v ss 22 p017 155 p063 94 p109 ? /p/ s 29 v ss 30 p018 154 p064 92 p110/ca0 27 v ss 35 p019 153 p065 90 p111/ca1 26 v ss 46 p020 152 p066 89 p112/ca2 25 v ss 53 p021 150 p067 88 p113/ca3 24 v ss 59 p022 149 p068 87 p114/ca4 23 v ss 66 p023 148 p069 84 p115/ca5 21 v ss 72 p024 147 p070 83 p116/ca6 20 v ss 79 p025 144 p071 82 p117/ra0 19 v ss 85 p026 143 p072 81 p118/ra1 16 v ss 91 p027 142 p073 80 p119/ra2 15 v ss 99 p028 141 p074 78 p120/ra3 14 v ss 105 p029 140 p075 77 p121/ra4 13 v ss 112 p030 136 p076 76 p122/ra5 12 v ss 119 p031 135 p077 75 p123/ra6 11 v ss 125 p032 134 p078 74 p124/c0 5 v ss 132 p033 133 p079 71 p125/c1 4 v ss 145 p034 130 p080 70 p126/we 3v ss 151 p035 129 p081 69 p127/strobe 2v ss 156 p036 128 p082 68 rce 6 v ss 162 p037 127 p083 67 tck 181 v ss 167 p038 126 p084/gt12 65 tdi 1 v ss 174 p039 124 p085/gt11 64 tdo 183 v ss 182 table 27. iqx128b [pqfp/184l] package pinout by name
iqx family data sheet february 2001 revision 6.2 53 6.11 iqx128b [pqfp/184l] package pinout by location pin# name pin# name pin# name pin# name 1tdi47v dd. pad2 93 v dd. pad1 139 gt0 2 p127/strobe 48 gt2 94 p063 140 p029 3 p126/we 49 p097/k1 95 p062 141 p028 4 p125/c1 50 p096/k2 96 p061 142 p027 5 p124/c0 51 p095/k3 97 p060 143 p026 6 rce 52 p094/k4 98 p059 144 p025 7gc153v ss 99 v ss 145 v ss 8v dd. pad2 54 p093/gc8 100 p058 146 v dd. pad1 9v ss 55 p092/gc9 101 p057 147 p024 10 gc0 56 p091/gc10 102 p056 148 p023 11 p123/ra6 57 p090/gc11 103 p055 149 p022 12 p122/ra5 58 p089/gc12 104 p054 150 p021 13 p121/ra4 59 v ss 105 v ss 151 v ss 14 p120/ra3 60 v dd. pad2 106 v dd. pad1 152 p020 15 p119/ra2 61 p088/gt8 107 p053 153 p019 16 p118/ra1 62 p087/gt9 108 p052 154 p018 17 v ss 63 p086/gt10 109 p051 155 p017 18 v dd. pad2 64 p085/gt11 110 p050 156 v ss 19 p117/ra0 65 p084/gt12 111 p049 157 v dd. pad1 20 p116/ca6 66 v ss 112 v ss 158 p016 21 p115/ca5 67 p083 113 p048 159 p015 22 v ss 68 p082 114 p047 160 p014 23 p114/ca4 69 p081 115 p046 161 p013 24 p113/ca3 70 p080 116 p045 162 v ss 25 p112/ca2 71 p079 117 p044 163 p012 26 p111/ca1 72 v ss 118 v dd 164 p011 27 p110/ca0 73 v dd. pad2 119 v ss 165 p010 28 v dd 74 p078 120 p043 166 p009 29 p109 ? /p/ s 75 p077 121 p042 167 v ss 30 v ss 76 p076 122 p041 168 v dd. pad1 31 p108 ? /gc2 77 p075 123 p040 169 p008 32 p107 ? /gc3 78 p074 124 p039 170 p007 33 p106 ? /gt4 79 v ss 125 v ss 171 p006 34 p105 ? /gt5 80 p073 126 p038 172 p005 35 v ss 81 p072 127 p037 173 p004 36 p104 ? /gt6 82 p071 128 p036 174 v ss 37 p103 ? /gt7 83 p070 129 p035 175 p003 38 p102 ? /gc4 84 p069 130 p034 176 p002 39 p101/gc5 85 v ss 131 v dd. x 177 p001 40 v dd. pad2 86 v dd. pad2 132 v ss 178 p000 41 v ss 87 p068 133 p033 179 trst* 42 p100/gc6 88 p067 134 p032 180 v dd. pad1 43 p099/gc7 89 p066 135 p031 181 tck 44 p098/k0 90 p065 136 p030 182 v ss 45 gt3 91 v ss 137 v dd. pad1 183 tdo 46 v ss 92 p064 138 gt1 184 tms table 28. iqx128b [pqfp/184l] package pinout by location
iqx family data sheet 54 revision 6.2 february 2001 6.12 iqx128b [pqfp/184l] package pinout figure 33. iqx128b [pqfp/184l] package pinout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 tdi p127/strobe p126/we p125/c1 p124/c0 rce gc1 v dd. pad2 v ss gc0 p123/ra6 p122/ra5 p121/ra4 p120/ra3 p119/ra2 p118/ra1 v ss v dd. pad2 p117/ra0 p116/ca6 p115/ca5 v ss p114/ca4 p113/ca3 p112/ca2 p111/ca1 p110/ca0 v dd p109 ? / p/s v ss p108 ? /gc2 p107 ? /gc3 p106 ? /gt4 p105 ? /gt5 v ss p104 ? /gt6 p103 ? /gt7 p102 ? /gc4 p101/gc5 v dd. pad2 v ss p100/gc6 p099/gc7 p098/k0 gt3 v ss tms tdo v ss tck v dd. pad1 trst* p000 p001 p002 p003 v ss p004 p005 p006 p007 p008 v dd. pad1 v ss p009 p010 p011 p012 v ss p013 p014 p015 p016 v dd. pad1 v ss p017 p018 p019 p020 v ss p021 p022 p023 p024 v dd. pad1 v ss p025 p026 p027 p028 p029 gt0 v dd.pad2 gt2 p097/k1 p096/k2 p095/k3 p094/k4 v ss p093/gc8 p092/gc9 p091/gc10 p090/gc11 p089/gc12 v ss v dd. pad2 p088/gt8 p087/gt9 p086/gt10 p085/gt11 p084/gt12 v ss p083 p082 p081 p080 p079 v ss v dd. pad2 p078 p077 p076 p075 p074 v ss p073 p072 p071 p070 p069 v ss v dd. pad2 p068 p067 p066 p065 v ss p064 gt1 v dd. pad1 p030 p031 p032 p033 v ss v dd. x p034 p035 p036 p037 p038 v ss p039 p040 p041 p042 p043 v ss v dd p044 p045 p046 p047 p048 v ss p049 p050 p051 p052 p053 v dd. pad1 v ss p054 p055 p056 p057 p058 v ss p059 p060 p061 p062 p063 v dd. pad1 top view i/o ports powered by v dd .pad2 i/o ports powered by v dd .pad1 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139
iqx family data sheet february 2001 revision 6.2 55 7.0 m echanical s pecification 7.1 iqx320 [pbga/416l] package dimensions figure 34. iqx320 [pbga/416l] package dimensions note: (1) use ? mm ? as the controlling dimension. bottom view (ball side) cross-sectional view 1.50 0.2 (0.059 .0079) 1.27 (0.050) mm. (in.) 0.60 (0.0236) 0.50 (0.0197) af ae ad ac ab aa y x w v u t r p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 af ae ad ac ab aa y x w v u t r p n m l k j h g f e d c b a 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 35 (1.378) 20.24 (0.797) top view iqx320 pb416 f5n42a usa pin a1 marking
iqx family data sheet 56 revision 6.2 february 2001 7.2 pqfp package dimensions figure 35. pqfp package dimensions note: (1) use ? mm ? as the controlling dimension package dimension table pqfp/304l pqfp/208l pqfp/184l inch mm inch mm inch mm a max 0.172 4.37 0.157 3.99 0.157 3.99 a1 min 0.011 0.28 0.010 0.25 0.010 0.25 max 0.019 0.47 0.017 0.43 0.017 0.43 a2 min 0.146 3.70 0.135 3.43 0.135 3.43 max 0.154 3.90 0.140 3.56 0.140 3.56 d min 1.669 42.40 1.195 30.40 1.219 31.01 max 1.685 42.80 1.215 30.91 1.238 31.49 d1 min 1.571 39.90 1.098 27.93 1.098 27.93 max 1.618 40.10 1.106 28.14 1.106 28.14 e min 1.669 42.40 1.195 30.40 1.219 31.01 max 1.685 42.80 1.215 30.91 1.238 31.49 e1 min 1.571 39.90 1.098 27.93 1.098 27.93 max 1.618 40.10 1.106 28.14 1.106 28.14 l min 0.020 0.50 0.018 0.46 0.029 0.74 max 0.028 0.75 0.030 0.76 0.041 1.04 b min 0.007 0.17 0.006 0.15 0.006 0.15 max 0.011 0.27 0.011 0.28 0.011 0.28 e bsc. 0.0197 0.50 0.0197 0.50 0.0197 0.50 table 29. pqfp package dimensions w x detail x top view side view detail w e e1 0.10 (0.004) 0 - 7 8 - 12 l e b a1 d1 d dimension in mm. (in.) a2 a
iqx family data sheet february 2001 revision 6.2 57 8.0 p ackage t hermal c haracteristics note: (1) thermal performance values are based on simulation data. package pin count jc (c/w) ja ( c/w) still air ja ( c/w) 200 ifpm ja ( c/w) 400 ifpm ja ( c/w) 600 ifpm pqfp 184 6.6 37.4 28.3 24.2 21.7 208 6.6 36.6 27.4 24.0 21.4 304 6.3 21.6 19.3 17.9 16.3 pbga 416 1.7 13.8 10.6 9.2 8.5 table 30. package thermal coefficients
iqx family data sheet 58 revision 6.2 february 2001 9.0 t ables for d etermining d ie p ad to i/o p ort p in m apping and l ocations of r eal sram c ell the following tables help determine the locations of the real sram cells in the switch matrix. the sram cell controlling the connection between i/o port ? i ? and i/o port ? j ? is determined as follows: get the index values corresponding to i/o port numbers ? i ? and ? j ? . if the index value for ? i ? is greater than index value for ? j ? , then the sram cell has the row (word) address i* and column (bit) address j*, otherwise it has row address of j* and column address of i *. the numbers i* and j* represent the i/o port locations on the die. ex 1: on the iqx160, the sram cell controlling the connection between i/o port 20 and i/o port 100 is at location: row addr = 2 0, col addr = 100; because the index for i/o port 20 is 82 , and it is greater than the index for i/o port 100 which is 79 . ex 2: on the iqx240b, the sram cell controlling the connection between i/o port 80 and i/o port 180 is at location: row addr = 241, col addr = 110; because the index value for i/o port 80 is 120 , and it is less than the index value for i/o port 180 which is 313 . note that the iqx240b is a bondout version of iqx320 die, and the i/o ports 80 and 180 on the device package are the i/o ports 110 and 241 respectively.
iqx family data sheet february 2001 revision 6.2 59 die pad and iqx320 i/o port iqx240b i/o port index die pad and iqx320 i/o port iqx240b i/o port index die pad and iqx320 i/o port iqx240b i/o port index die pad and iqx320 i/o port iqx240b i/o port index 0- 240 30 162 80 - 0 120 90 160 10 641 31 166 81 60 4 121 91 164 2- 10 42 32 170 82 - 8 122 92 168 31 14 43 33 174 83 61 12 123 93 172 4- 18 44 34 178 84 - 16 124 94 176 52 22 45 35 182 85 62 20 125 95 180 6- 26 46 36 186 86 - 24 126 96 184 73 30 47 37 190 87 63 28 127 97 188 8- 34 48 38 194 88 - 32 128 98 192 94 38 49 39 198 89 64 36 129 99 196 10 - 42 50 40 202 90 - 40 130 100 200 11 5 46 51 41 206 91 65 44 131 101 204 12 - 50 52 42 210 92 - 48 132 102 208 13 6 54 53 43 214 93 66 52 133 103 212 14 - 58 54 44 218 94 67 56 134 104 216 15 7 62 55 45 222 95 68 60 135 105 220 16 8 66 56 - 226 96 - 64 136 106 224 17 9 70 57 46 230 97 69 68 137 107 228 18 10 74 58 - 234 98 - 72 138 108 232 19 11 78 59 47 238 99 70 76 139 109 236 20 12 82 60 - 242 100 - 80 140 - 240 21 13 86 61 48 246 101 71 84 141 110 244 22 14 90 62 - 250 102 72 88 142 - 248 23 15 94 63 49 254 103 73 92 143 111 252 24 - 98 64 - 258 104 74 96 144 - 256 25 16 102 65 50 262 105 75 100 145 112 260 26 17 106 66 - 266 106 76 104 146 - 264 27 18 110 67 51 270 107 77 108 147 113 268 28 19 114 68 - 274 108 78 112 148 - 272 29 20 118 69 52 278 109 79 116 149 114 276 30 21 122 70 - 282 110 80 120 150 - 280 31 22 126 71 53 286 111 81 124 151 115 284 32 23 130 72 - 290 112 82 128 152 - 288 33 24 134 73 54 294 113 83 132 153 116 292 34 - 138 74 - 298 114 84 136 154 - 296 35 25 142 75 55 302 115 85 140 155 117 300 36 26 146 76 56 306 116 86 144 156 - 304 37 27 150 77 57 310 117 87 148 157 118 308 38 28 154 78 58 314 118 88 152 158 - 312 39 29 158 79 59 318 119 89 156 159 119 316 table 31. iqx320 and iqx240b i/o port pin mapping
iqx family data sheet 60 revision 6.2 february 2001 160 - 319 200 149 159 240 - 317 280 - 157 161 120 315 201 150 155 241 180 313 281 208 153 162 - 311 202 151 151 242 181 309 282 - 149 163 121 307 203 152 147 243 182 305 283 209 145 164 - 303 204 153 143 244 - 301 284 - 141 165 122 299 205 154 139 245 183 297 285 210 137 166 - 295 206 155 135 246 - 293 286 - 133 167 123 291 207 156 131 247 184 289 287 211 129 168 - 287 208 157 127 248 - 285 288 - 125 169 124 283 209 158 123 249 185 281 289 212 121 170 - 279 210 159 119 250 - 277 290 - 117 171 125 275 211 160 115 251 186 273 291 213 113 172 - 271 212 161 111 252 - 269 292 - 109 173 126 267 213 162 107 253 187 265 293 214 105 174 - 263 214 163 103 254 188 261 294 - 101 175 127 259 215 164 99 255 189 257 295 215 97 176 - 255 216 165 95 256 190 253 296 216 93 177 128 251 217 166 91 257 191 249 297 217 89 178 - 247 218 167 87 258 192 245 298 218 85 179 129 243 219 168 83 259 193 241 299 219 81 180 - 239 220 169 79 260 194 237 300 220 77 181 130 235 221 170 75 261 195 233 301 221 73 182 131 231 222 - 71 262 - 229 302 222 69 183 132 227 223 171 67 263 196 225 303 223 65 184 133 223 224 - 63 264 - 221 304 224 61 185 134 219 225 172 59 265 197 217 305 225 57 186 135 215 226 - 55 266 - 213 306 226 53 187 136 211 227 173 51 267 198 209 307 227 49 188 137 207 228 - 47 268 199 205 308 228 45 189 138 203 229 174 43 269 200 201 309 229 41 190 139 199 230 - 39 270 201 197 310 230 37 191 140 195 231 175 35 271 202 193 311 231 33 192 141 191 232 - 31 272 203 189 312 232 29 193 142 187 233 176 27 273 204 185 313 233 25 194 143 183 234 - 23 274 - 181 314 234 21 195 144 179 235 177 19 275 205 177 315 235 17 196 145 175 236 - 15 276 - 173 316 236 13 197 146 171 237 178 11 277 206 169 317 237 9 198 147 167 238 - 7 278 - 165 318 238 5 199 148 163 239 179 3 279 207 161 319 239 1 die pad and iqx320 i/o port iqx240b i/o port index die pad and iqx320 i/o port iqx240b i/o port index die pad and iqx320 i/o port iqx240b i/o port index die pad and iqx320 i/o port iqx240b i/o port index table 31. iqx320 and iqx240b i/o port pin mapping (continued)
iqx family data sheet february 2001 revision 6.2 61 die pad and iqx160 i/o port iqx128b i/o port index die pad and iqx160 i/o port iqx128b i/o port index die pad and iqx160 i/o port iqx128b i/o port index die pad and iqx160 i/o port iqx128b i/o port index 00 240 - 080 64 159 120 96 157 11 641 - 481 65 155 121 97 153 22 10 42 32 882 66 151 122 98 149 33 14 43 33 12 83 - 147 123 - 145 44 18 44 34 16 84 67 143 124 - 141 55 22 45 35 20 85 68 139 125 99 137 66 26 46 36 24 86 69 135 126 100 133 77 30 47 - 28 87 70 131 127 101 129 88 34 48 37 32 88 71 127 128 102 125 99 38 49 38 36 89 - 123 129 - 121 10 10 42 50 39 40 90 72 119 130 - 117 11 - 46 51 40 44 91 73 115 131 103 113 12 - 50 52 41 48 92 74 111 132 104 109 13 11 54 53 - 52 93 75 107 133 105 105 14 12 58 54 42 56 94 76 103 134 106 101 15 13 62 55 43 60 95 - 99 135 - 97 16 14 66 56 44 64 96 77 95 136 - 93 17 - 70 57 45 68 97 78 91 137 107 89 18 - 74 58 46 72 98 79 87 138 108 85 19 15 78 59 - 76 99 80 83 139 109 81 20 16 82 60 47 80 100 81 79 140 110 77 21 17 86 61 48 84 101 - 75 141 111 73 22 18 90 62 49 88 102 82 71 142 112 69 23 - 94 63 50 92 103 83 67 143 113 65 24 - 98 64 51 96 104 84 63 144 114 61 25 19 102 65 - 100 105 85 59 145 115 57 26 20 106 66 52 104 106 86 55 146 116 53 27 21 110 67 53 108 107 - 51 147 - 49 28 22 114 68 54 112 108 87 47 148 117 45 29 - 118 69 55 116 109 88 43 149 118 41 30 - 122 70 56 120 110 89 39 150 119 37 31 23 126 71 - 124 111 90 35 151 120 33 32 24 130 72 57 128 112 91 31 152 121 29 33 25 134 73 58 132 113 - 27 153 122 25 34 26 138 74 59 136 114 92 23 154 123 21 35 27 142 75 60 140 115 93 19 155 - 17 36 28 146 76 61 144 116 94 15 156 124 13 37 29 150 77 62 148 117 95 11 157 125 9 38 30 154 78 63 152 118 - 7 158 126 5 39 31 158 79 - 156 119 - 3 159 127 1 table 32. iqx160 and iqx128b i/o port pin mapping
iqx family data sheet 62 revision 6.2 february 2001 10.0 c omponent a vailability and o rdering i nformation the following table lists the iqx devices and the different package options, and speed grades available. * pb=plastic ball grid array, pq=plastic quad flat pack package pins 184 208 304 416 type pqfp pqfp pqfp pbga code pq184 pq208 pq304 pb416 iqx320 -12 x -10 x iqx240b -12 x -10 x iqx160 -10 x -7 x iqx128b -10 x -7 x table 33. component availability device speed package* ordering# iqx320 -12 pb 416 iqx320-pb416 -10 pb 416 iqx320-10pb416 iqx240b -12 pq 304 iqx240b-pq304 -10 pq 304 iqx240b-10pq304 iqx160 -10 pq 208 IQX160-PQ208 -7 pq 208 iqx160-7pq208 iqx128b -10 pq 184 iqx128b-pq184 -7 pq 184 iqx128b-7pq184 table 34. ordering information
iqx family data sheet 63 revision 6.2 february 2001 11.0 iqx f amily at a g lance feature iqx320 iqx240b iqx160 iqx128b number of usable i/o port pins 320 240 160 128 switch matrix size 320 lines 240 lines 160 lines 128 lines programmable i/o port attributes signal direction in, out, bidir in, out, bidir in, out, bidir in, out, bidir dataflow flow-through, latched, clocked flow-through, latched, clocked flow-through, latched, clocked flow-through, latched, clocked control signals clock, clock enable, input tristate, output tristate clock, clock enable, input tristate, output tristate clock, clock enable, input tristate, output tristate clock, clock enable, input tristate, output tristate number of clock control pins dedicated 4 4 2 2 shared with i/o port pins 9 9 11 11 number of tristate control pins dedicated 5 5 4 4 shared with i/o port pins 8 8 9 9 i/o ports used by rapidconfigure interface 23 / 22 23 / 22 21/20 19/18 pin-to-pin delay 10 ns 10 ns 7.5 ns 7.5 ns nrz data rate 180 mbs 180 mbs 200 mbs 200 mbs maximum clock frequency 100 mhz 100 mhz 133 mhz 133 mhz i/o current drive 12 ma 12 ma 12 ma 12 ma i/o voltage 3v and/or 5v 3v and/or 5v 3v and/or 5v 3v and/or 5v process 0.6 0.6 0.6 0.6 packages 416 pbga 304 pqfp 208 pqfp 184 pqfp table 35. iqx family at a glance
iqx family data sheet 64 revision 6.2 february 2001 12.0 r evision h istory date version no. description 11/17/00 6.1 in table 7, ? i/o configuration register contents ? , the registered input w/tristate segment 0 bit was changed from 0000 1111 to 000*****; the output segment 0 bit was changed from 000***** to 0000 1111. 2/2/2001 6.2 changes to table 11, ? iqx family at a glance ? : pin-to-pin delay from 7.5 ns to 10 ns and maximum clock frequency from 133 mhz to 100 mhz for iqx320 and iqx240b; removed the following package sizes: 391 pbga from iqx320 304 mquad from iqx240b 208 mquad from iqx160 184 mquad from iqx128b table 36. revision history
iqx family data sheet 65 revision 6.2 february 2001 13.0 p roduct s tatus d efinitions i-cube ? is a registered trademark and rapidconnect, rapidconfigure, activearray, implieddisconnect, iq, iqx, msx, msxpro, ocx and psx are trademarks of i-cube, inc. all other trademarks or registered trademarks are the property of their respective holders. i-cube, inc., does not assume any liability arising out of the applications or use of the product described herein; nor does it convey any license under its patents, copyright rights or any rights of others. the information contained in this document is believed to be current and accurate as of the publication date. i-cube reserves t he right to make changes, at any time, in order to improve reliability, function, performance or design in order to supply the best product poss ible. i-cube assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made. life support applications i-cube products are not designed for use in life support appliances, devices, or systems where malfunction of an i-cube product can reasonably be expected to result in personal injury. i-cube customers using or selling i-cube products for use in such application do so at t heir own risk and agree to fully indemnify i-cube for any damages resulting from such improper use or sale. this product is protected under the u.s. patents: 5202593, 5282271, 5426738, 5428750, 5428800, 5465056, 5530814, 5559971, 56257 80, 5710550, 5717871, 5734334, 5754791, 5781717, 5790048. additional patents pending. iqx family data sheet ? revision 6.2, february 2001 previously printed as iqx family data sheet ? revision 6.1, november 2000 copyright ? 1992-2001 i-cube, inc. all rights reserved. unpublished ? rights reserved under the copyright laws of the united states. use of copyright notices is precautionary and does not imply publication or disclosure. i-cube ? , inc. 2605 s. winchester blvd. campbell, ca 95008, usa phone: +(408) 341-1888 fax: +(408) 341-1899 email: marketing@icube.com internet: http://www.icube.com iqx family data sheet revision 6.2, february 2001 document # mkt-iqxfamily-ds data sheet identification product status definition advanced formative or in design this data sheet contains the design specifications for product development. specification may change in any manner without notice. preliminary preproduction product this data sheet contains the preliminary data, and supplementary data will be published at a later date. i-cube reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. no identification full production this data sheet contains final specifications. i-cube reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. obsolete no longer in production this data sheet contains specifications for a product that has been discontinued by i-cube. the data sheet is provided for reference information only.

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